FPGA practice mimes 22:32 (2006.10.03:5 fpga#15 tech_notes#286 research#91 xxxxx_at_piksel_notes#42)

the high- low- level overlap we are interested in

in terms of a methodology of description (code, the diagram, a description of behaviour, software generation of HDL)

Lisp CPU (cell) structure - ie. representation - in the CPU: 21:19 (2006.10.03:4 tech_notes#285 fpga#14 lispcpu#2 research#90 xxxxx_at_piksel_notes#41)

after: Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode

Guy Steele and Gerald Sussman

(http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT


1] Architecture reflectes language structure

2] The overlap of high level and machine language is also dictated by necessity to manipulate program as data

3] Programs are represented as nested Lisp data structures -> as a tree of linked records subject to a recursive tree walk

4] Lists are represented by records each of which contains 2 pointers to other records - car and cdr

5] The type field associated with each pointer is used to encode opcodes and return addresses

6] p17 implementation:

7] Two consecutive words of memory hold a list cell - each word can hold a type field and an address field (an address referenced within linear memory)

8] The evaluator and the storage manager as individual processors each with a state machine controller and a set of registers

contents of any register is address field and type field

9] p32 evaluation and procedure call (type 6):

We have a 3-bit type field which provides 8 opcodes (recall 7 as quotation) - address part of a word has different function depending on type (6 is procedure call).


The evaluation of type 4 (procedure) results in a pointer to the newly allocated word pair. This pointer has type 3 (closure). The car of the pair contains the cdr of the procedure: this is the code body of the procedure. The cdr of the pair contains the current environment.


A procedure call (type 6) is the most complicated... It is a list of indefinite length, chained together by cdr pointers. Each cdr pointer except the last MUST have type 0 (list). The last cdr pointer should have a zero address and a non-ZERO type. This last type specifies the operation to be performed. In CDRing down the list, SIMPLE evaluates each of the expressions in the car, saving the resulting values. These values are available as arguments to the operation to be performed.

operations in tyoe here such as car, cdr, cons, atom, progn, list and funcall

10] further question of recursion in hardware by way of closures:

A closure combines the code of a function with a special lexical environment bound to that function (scope).

From gluion manual (for FPGA ref): 20:31 (2006.10.03:3 tech_notes#284 fpga#13)

5v (TTL a la 74xxxx) to 3.3v (FPGA)

The second thing to do is to insert resistors between the output signals of your 5V circuitry and the gluion's 3.3V inputs. 1k Ohm will do. Furthermore you will need a clamping diode with the anode at your input pin, the cathode tied to 3.3V.

also for matrix 8x8 (chess computer interface):

Some details on the above schematic for the curious: the basic principle of a switch matrix is time-division multiplexing. This is denoted by the pulse diagrams to the left side of the SMR pins where you can see that first SMR0 is pulled low while all other SMR lines are kept high. The system then checks at which SMC pins the pulse arrives, i.e. it now knows which buttons of row 0 are held down. The process is then repeated for each row before re-starting the cycle. This is done at such a high frequency that even the shortest button closure is registered.

The resistors above the SMC pins are internal to the FPGA, i.e. you don't have to supply them yourself. They were implemented to keep the inputs from floating. As a consequence the Switch Matrix is operating in negated mode, i.e. diodes being "reversed" and pulses going down instead of up. However, this should be of no concern to the user, as long as you connect the diodes as shown above.

see: http://www.glui.de/prod/gluion/manual/gManMain.html

sync and VGA fine 20:05 (2006.10.03:2 tech_notes#283 research#89)

using FPGA for H and V sync

(for RGB from Schmitt triggers remember to link GND from board(s) to box)

Our FPGA/VGA experiment is in: 17:05 (2006.10.03:1 tech_notes#282 fpga#12)


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