--> ap/xxxxx

* __

Amateur Scientist - DIY FET/home-made transistor Scientific American June 1970: (2008.04.15:3 materials#1 research#140)

Roger Baker:

"Recently," Baker writes, "I learned of a governing principle known as Murphy's first law of biology. It states: 'Under any given set of environmental conditions an experimental animal behaves as it damn well pleases.' The same law appears to govern the behavior of thin metallic films, at least those I make. Some of my 'transistors' make dandy thermistors, and an occasional photocell works better as a fluorescent screen. There might be fewer surprises if I used better tools and had more experience, but some of the fun might also be lost. The techniques used by industry for making thin films are not beyond the reach of amateurs, but they require vacuum pumps, electronic heating device and controlled sources of high voltage that are costly and inconvenient to use. Thin films can also be deposited chemically. I use this method.

Roger Baker's apparatus for depositing metallic films on glass

"Most of my films are deposited on substrates of glass. Usually I heat the glass and spray the surface with a solution of selected chemicals. The sprays react immediately to form the film.

"Films can be annealed in various atmospheres and at various temperatures that alter their composition, structure and properties. The properties of a deposited film can also be modified by recrystallization, by solid-state diffusion or by a vapor-phase displacement reaction. These procedures are much simpler to perform than their imposing names suggest. The properties of films can be radically altered by the addition of minute amounts of impurities, either when they are formed or by subsequent diffusion.

The microstructure of the substrate can also influence the properties of a film. For example, calcium sulfide forms an amorphous film when sprayed on a metal surface, but on glass it becomes a crystalline film.

"The required tools include an electric hot plate, a diamond point for cutting thin glass, an atomizer and a microammeter. Desirable accessories are a fume hood, which can be improvised if you have an exhaust fan, an oven thermometer for measuring the temperature of the hot plate, a triple-beam chemical balance, a pair of tweezers and chemical glassware for preparing solutions. For substrates I use mostly cover glasses of 35-millimeter Kodak slides, which I cut into small rectangles with the diamond point. These glasses can be heated (up to 600 degrees Celsius) and sprayed without breaking. Thin disks of alumina can be used at higher temperatures. I salvage them from discarded vacuum tubes. I immerse the glass slides for three days in a solution of one part by volume of nitric acid to 12 parts of distilled water. The acid leaches sodium and calcium ions from the glass, exposing a surface layer of relatively pure silica.

"A great variety of semiconducting oxide films can be made by thermally decomposing the resinate salts of metals. Resinate salts are prepared by stirring an excess of pure granulated resin into a one-normal (1 N) solution of sodium hydroxide. The solution turns milky as it cools. Pour off and retain the milky solution. To make a metal resinate, reheat the milky sodium-resinate solution and combine it with a weak solution of the metal salt, stirring the mixture vigorously.

"A relatively large volume of sodium resinate reacts with a small volume of metal salt. An excess of sodium is indicated by a pH of 8 or more. Add metal salt to lower the pH. The desired metal resinate appears as a thick precipitate.

"Filter the solution to recover the precipitate and wash it thoroughly with hot distilled water. Spread the moist filter cake and dry it at a temperature of about 50 degrees C. Dissolve the dried material in an organic solvent such as turpentine. Allow the sediment to settle. Use the clear upper layer for experiments.

"With a disposable capillary tube apply a few drops of the clear fluid to the center of a prepared cover glass and rock the glass to spread the fluid into a uniform film that extends to the edges. Heat the coated glass on the hot plate. The film will smoke and turn dark. In time, at a temperature that depends on the nature of the resinate, the dark color will clear, leaving a thin film of metallic oxide. The cover glass can then be scribed with the diamond point and broken into rectangles of convenient size for further processing and experimentation.

"Sulfide films can be formed directly from a number of oxide films. Sprinkle a few milligrams of sulfur on the back side of the coated substrate, wrap it with several layers of aluminum foil, fold the ends of the foil over the package and heat the package. The hot vapor of the sulfur will react with many oxides to form adherent films with interesting electrical properties. Two drops of different resinates can be allowed to diffuse partially together so that the properties of various ratios of the two can be explored.

"So far I have experimented with gold, nickel, cobalt, copper, iron, manganese, silver, indium, chromium, zinc and cadmium resinates. The salts of noble metals decompose into metallic films instead of oxides. They can be used for making electrical connections between various films of oxide previously applied to a substrate.

"The preparation of a field-effect transistor illustrates a typical experimental procedure. The substrate, which has been treated with nitric acid solution, is first coated with a film of cadmium sulfide. With distilled water prepare 500 milliliters of a stock solution containing .01 molar (.01 M) thiourea and .01 M cadmium chloride.

"Place the substrate inside a 250-milliliter beaker so that it rests diagonally against the side of the beaker. Cover the substrate with stock solution and slowly add concentrated ammonium hydroxide until the mixture turns faintly cloudy and then clears. Cover the beaker and put it in a double boiler. Heat the vessel slowly and boil for about 15 minutes. The contents of the beaker will turn yellow-orange, indicating the precipitation of cadmium sulfide.

'Pour off the contents and replace them with distilled water. Swab the substrate lightly with a tuft of absorbent cotton to remove adhering particles of cadmium sulfide. Rinse the substrate with distilled water. Repeat the entire procedure to double the thickness of the film, after which you can clean the beaker with hydrochloric acid.

"Bake the substrate in air at 500 degrees C. for 30 minutes. The color of the hot substrate will gradually change from yellow to red and, as it cools, to a deeper shade of orange. With the diamond point scribe and break the cooled glass into rectangular chips 1/4 inch wide and 1/2 inch long.

"The transistor requires two contacts that function as electrodes, one a source and the other a drain. The electrodes are conveniently made of indium, a soft metal that can be pressed into firm contact with the film. Indium is available from dealers in chemicals. Place a small pellet of indium on clean plate glass and roll it into thin foil with a short length of clean glass tubing. Transfer the foil to a yielding surface such as glossy white cardboard and, by pressing straight down with a sharp razor blade, cut the metal into strips about 1/32 inch wide and 1/4 inch long.

Sequential steps in making a thin-film transistor

"With a sewing needle maneuver two of the strips to a clear portion of the paper so that they are parallel and spaced about 1/16 inch apart. Lay one of the coated chips over the strips so that the ends of the strips are even with one end of the chip. Press the chip firmly and evenly against the metal. The strips will adhere lightly to the film. Burnish them firmly into place by turning the chip strip side up on the plate glass, covering it with a glossy magazine cover and rubbing it with a fingernail. Place a small dab of conductive silver paste on the outer end of each indium strip [see illustration at right]. The dabs serve as terminals for connecting the electrode device to a power source.

"A layer of insulation is applied to the film and the indium strips in preparation for adding the third electrode, which is known as the gate. With a sewing needle apply a thin, uniform layer of vinyl cement by stroking the cement across the upper surface of the device. Do not coat the silver terminals. When the cement dries, apply a coat of silver paste over the insulation. Do not let the silver make contact with the cadmium sulfide film, the indium foils or the source and drain terminals. This completes the gate electrode.

"Finally, to protect the active region of the device coat the upper surface with a layer of silicone rubber that cures in air. This material is available from dealers in hardware. Leave one small region of the gate electrode exposed. This small area will be used for making electrical contact with the gate. Do not coat the source and drain terminals with rubber.

"To operate the device improvise a test fixture such as the one shown in the accompanying illustration [left] for holding the transistor and connecting it to a battery. Power is applied to the source and drain electrodes by a ninevolt transistor battery that is connected in series with a 10,000-ohm resistor and a 0-50 microammeter. If the transistor is reasonably good, the meter will indicate a current of about 10 microamperes. This is called the leakage current.

"Connect a one-megohm resistor between the gate electrode and the positive terminal of the battery. The positively charged gate will attract free carrier electrons into the cadmium sulfide film. Current through the film should rise to about 50 microamperes, indicating that the transistor is a so-called N-channel device and that it is operating in the enhancement mode. The gate electrode draws little current.

"If negative charge is now applied to the gate by transferring the one-megohm resistor to the negative terminal of the battery, current in the source-drain circuit should fall below 10 microamperes. The transistor is now operating in the depletion mode. I do not know why some homemade transistors work better than others. I suspect that their performance may be related to the crystalline structure of the films.

"Capacitors can be made by sandwiching insulation between films, resistors by etching away portions of film to form narrow conducting paths, photocells by doping cadmium sulfide with trace amounts of silver, copper or manganese. Films of zinc sulfide fluoresce strongly. Of course, devices are available on the market that work better than those one can make at home, but mine are better playthings.

"Certain hazards must be mentioned. Metallic salts and acids are toxic. Work either in a fume hood or outdoors when you spray chemicals onto a hot substrate. Wear gloves and an apron of neoprene when you handle acids. Remember that chemicals are hazardous and handle them accordingly."

Bibliography

THIN FILM MICROELECTRONICS: THE PREPARATION AND PROPERTIES OF COMPONENTS AND CIRCUIT ARRAYS. Edited by L. Holland. John Wiley & Sons Inc., 1965.

diverse notes - James Clerk Maxwell Lewis Carroll: (2008.03.31:1)

1] James Clerk Maxwell:

Reading The Demon in the Aether (The life of... by Martin Goldman).

Concerning A Dynamical Theory of the Electromagnetic Field (1864), Goldman writes:

What Maxwell had done in his new paper he compared to being a bell-ringer:

In an ordinary belfry, each bell has one rope which comes down through a hole in the floor to the bellringer's room. But suppose that each rope, instead of acting on one bell, contributes to the motion of many pieces of machinery, and that the motion of each piece is determined not by the motion of one rope alone, but by that of several, and suppose, further that all this machinery is silent and utterly unknown to the men at the ropes, who can only see as far as the holes in the floor above them.

[p.169] concerning optical instruments:

He dug up, revived and developed an old theorem of Roger Cotes to consider instruments as being 'black boxes'.

[p.196] concerning the aether and J.J Thompson's reaction:

Maxwell's electromagnetic field equations seemed to by-pass the aether, he might profess still to believe in an aether, but it was no longer necessary to him to explain light. His was a new and utterly disturbing sort of theory, in which he talked of waves, but did not care what was doing the waving. What Maxwell has done was introduce abstract, formal mathematical modelling by differential equations, as the basis of a physical understanding of the phenomena... It is not surprising that Thomson was perturbed by this.

I never satisfy myself until I can make a mechanical model of a thing. If I can make a mechanical model, I understand it... and that is why I cannot get the electromagnetic theory of light.

also to note:

David Hughes experiment [p.197] to detect electromagnetic radiation

Henry Cavendish

82] Antonin Artaud and Lewis Carroll:*

The Walrus and the Carpenter (Annotated Alice p.236)

...

But answer was there none

And this was scarcely odd, because

They'd eaten every one.

///

Following Deleuze - Logique du sens [Thirteenth Series of the Schizophrenic and the Little Girl]

Artaud oeuvres:

p.1012+ Lettres de Rodez a Henri Parisot 20/22 September 1945 (concerning the earlier translations/adaptations including fragment of Jabberwocky)

p.913 Adaptations de Lewis Carroll:

Variations a propos d'un theme

L'Arve et L'Aume [Tentative anti-grammaticale contre Lewis Carroll]

Action at a distance: (2007.02.13:2)

de Forest, the transistor:

And finally, since 1906, when Lee de Forest invented the valve amplifier, we have the possibility to modulate the low frequencies of music, such as record grooves, as electromagnetic high frequencies, to thus transmit without substance, so that Tchaichovskyssss overture can sound out on any simple transistor radio on any cross-country bus.

[Friedrich Kittler. Pynchon and Electro-mysticism]

see also Thomas Pynchon. Against the Day. p29

The relay or transistor as enabling (digital) computation - a certain form of computation in relation to a simulation (of the world) - the action at a distance of such components implies this separation of/for another world (the seperate interiority of execution - a question of a taking place, a "where" for the viral - in my system, in the executable heart of the machine - hiding in memory. a ghost resident).

also (spooky) action at a distance within physics (according to Einstein). see:

http://en.wikipedia.org/wiki/Action_at_a_distance_(physics)

from physics page above:

Current physical theories incorporate the upper limit on propagation of interaction as one of their basic building blocks, hence ruling out instantaneous action-at-a-distance. While a naive interpretation of quantum mechanics appears to imply the ability to send signals faster than the speed of light, careful reasoning about these cases shows that no physical signals are actually being sent. Einstein coined the term "spooky action at a distance" to describe these situations, which exhibit quantum entanglement. Relativistic quantum field theory requires interactions to propagate at less than the speed of light, so quantum entanglement cannot be used for faster-than-light-speed propagation of matter, energy, or information. However, it must be understood that a change to one entangled particle does indeed affect the other instantaneously, but this is only known after the experiment is performed and notes are compared, therefore there is no way to actually send information faster than the speed of light. Einstein could not believe this, and therefore he proposed, along with Boris Podolsky and Nathan Rosen, a thought experiment called the EPR paradox. John Bell derived an inequality that showed a testable difference between the predictions of quantum mechanics and local hidden variables theories. Experiments testing Bell-type inequalities in situations analogous to EPR's thought experiments have been consistent with the predictions of quantum mechanics, giving strong evidence for nonlocality.

... such action at a distance as implying (remote) control - the relay, the transistor.

Containment and doubling in technology (2007.02.09:2)

as a heading

(or for Emacs Lisp work: a ghost buffer using perhaps clone-buffer function - a doppelganger across another side of...)

and more pipes: (2007.01.22:3 pipes#2 research#4)

1] tee and tpipe app

2] using lsof to find open pipes and then cat file descriptor a la cat /proc/18952/fd/29

see also:

http://www-128.ibm.com/developerworks/aix/library/au-lsof.html

http://www.vias.org/linux-knowhow/bbg_sect_08_02_03.html

http://www.math.temple.edu/~rivin/software/schemeprogs/bipipes.sc

pipes and pipes... (2007.01.22:2 pipes#1 research#3 workshop_notes#1)

for workshopping also:

1] Listenpipe: http://www.vanheusden.com/listenpipe/ - lp01

2] Pd. piperead~ and pipewrite~ externals and our sample patches for plenum

3] pipes in ap0202 software

4] pipes in our own commandline software: OSC, neuronal, devdisplay, jekyll software

5] pipes in promiscuOS: promiscuOS_notes#7 (pipe.c in the kernel)

6] pluggability: plugging

7] pipes and process: OS -

pipes p.776+ (Understanding Linux Kernel) also the pipe code we found: lp-01 which copies file descriptors (pipe is only accessible to parent process). FIFO allows for arbitrary piping and is associated with a kernel buffer.

8] proposed leaking pipes and pools

9]

lsof | grep FIFO

10] (netcat) and for workshop:

1) basic understanding GNU/Linux and networking:

d) cat, dd and ls

i) what are pipes and how they work

j) what is a FIFO and how we can use named pipes

3) audio on Linux

a) what is a device?

b) what is /dev/dsp and how we can input and output on the command line

c) how we can use stuff like cat with /dev/dsp

d) what is sample rate. 8 bit/16 bit audio

3) netcat and pd

a) is basically networked cat but need to understand ports

b) maybe also pd in relation to netcat and pipes

c) how we can interface ap to pd

see also unix

re-examining supercollider/scheme... (2007.01.22:1)

From Rohan Drape:

http://slavepianos.org/rd/r/darcsweb.cgi

1] rsc - rsc SuperCollider Client

rsc 1 is a set of extensions to the PLT Scheme implementation 2 that facilitate using Scheme as a client to the SuperCollider 3 synthesis server. The rsc interaction environment is written for GNU Emacs 4.

http://www.slavepianos.org/rd/sw/sw-01/

2] ssc - S-Expression SuperCollider

ssc implements an s-expression read syntax for the SuperCollider language.

http://www.slavepianos.org/rd/sw/sw-40/

Oslo expansion: (2007.01.15:3 research#133 osloexpansion#1)

Oslo expansion:

An expansion of the xxxxx_interface_pres presentation:

interrogation walking:

low

to->

high level

wonderland environment and rabbit-holed promiscuOS

further embedded texts could include calculating space, lispcpu MIT text...

rotational devices: (2007.01.15:1)

phenakistiscope from Joseph Plateau

based on Faraday's Wheels

anorthoscope also by Plateau

praxinoscope from Charles-Emile Reynaud

based on the zoetrope

and inspiring Reynaud's Theatre Optique:

... the Black Maria film studio itself

... if the idea was for still pictures to move, why there had to be a better way than this elaborate contraption of gear-trains and multiple lenses and matching up speeds and watchmaker's fancywork to get each frame to stop a split-second and all. There had to be somthing more direct, something you could do with light itself.

Thomas Pynchon. Against the Day. p451

also p457... (time and gravity: Gravity pulls along the third dimension, up to down, time pulls along the fourth, birth to death)

Quack: enhances Emacs support for Scheme programming. (2007.01.10:1 research#131 scheme#3 emacs#13 tech_notes#4)

http://www.neilvandyke.org/quack/

1] download and (require 'quack) in .emacs

http://www.neilvandyke.org/quack/quack.el

2] default fontlock for ;;; comments (three semicolons) is blue text-invisible bars. change this with:

(setq quack-fontify-threesemi-p nil)

3] Key bindings:

;;     The key bindings that Quack adds to `scheme-mode' include:
;;
;;         C-c C-q m   View a manual in your Web browser.
;;         C-c C-q k   View the manual documentation for a keyword
;;                     (currently only works for PLT manuals).
;;         C-c C-q s   View an SRFI. (Scheme Requests for Implementation)
;;         C-c C-q r   Run an inferior Scheme process.
;;         C-c C-q f   Find a file using context of point for default.
;;         C-c C-q l   Toggle `lambda' syntax of `define'-like form.
;;         C-c C-q t   Tidy the formatting of the buffer.

towards a scrying (Scheme) embedded interpreter (2007.01.09:1 research#130 interpreter#1 scrying#1)

with a nod to Wilfried's article: http://socialfiction.org/index.php?tag=scrying

and the mention of the mirror and timed revolution (dream machine) returning us to the film machine/Black Maria - itself a black, absorbing density (the black velvet of the magic trick (Pynchon AtD)) in relation to reflecting (of life)

research centre update: (2007.01.08:3)

xxxxx_research_institute

SICP code from Chapter 4: Metalinguistic Abstraction (2007.01.05:4 lisp#5 research#128 scheme#2)

Running the meta-circular evaluator on MzScheme requires a few changes to the code:

to figure out:

(define (eval exp env)
  (cond ((self-evaluating? exp) exp)
        ((variable? exp) (lookup-variable-value exp env))
        ((quoted? exp) (text-of-quotation exp))
        ((assignment? exp) (eval-assignment exp env))
        ((definition? exp) (eval-definition exp env))
        ((if? exp) (eval-if exp env))
        ((lambda? exp)
         (make-procedure (lambda-parameters exp)
                         (lambda-body exp)
                         env))
        ((begin? exp) 
         (eval-sequence (begin-actions exp) env))
        ((cond? exp) (eval (cond->if exp) env))
        ((application? exp)
         (apply (eval (operator exp) env)
                (list-of-values (operands exp) env)))
        (else
         (error "Unknown expression type -- EVAL" exp))))

;;;

(define (make-procedure parameters body env)
  (list 'procedure parameters body env))


list expression arrives by default at apply which separates into operator and operands by way of car and cdr - this is sent again to eval with the environment - primitive is looked up as variable and we have as procedure:

(primitive #)

which tests correctly by way of tagged-list? as a primitive:

<(define (tagged-list? exp tag)
  (if (pair? exp)
      (eq? (car exp) tag)
      #f))

which is then applied using underlying Scheme apply

Scheme Machine: (2007.01.05:3 research#127 lispcpu#6)

http://www.cs.indiana.edu/hmg/schemachine-wp.htm

ActorNet (2007.01.05:2)

ActorNet is a mobile agent platform for Wireless Sensor Networks (WSNs). It provides a scheme-like simple syntax, coordination services, and many useful library of modules so that applications for WSNs can be easily developed.

http://yangtze.cs.uiuc.edu/~ykwon4/

The given instruction (2007.01.05:1)

[in some ways concerns uniting xxxxx projects such as promiscuOS (evident process manipulation and memory leaks)

and recent atmegascheme or lispcpu work - that in some ways it is not a Lisp CPU (whatever that would be) but rather only an abstraction of a flat memory model, a simulation as is all hardware

and Sadean life_coding at the same time.

the data sheet (the hardware), a series of microcodes (Design of Lisp Based processors), assemblers (SICP p520 for example), interpreters (SICP, elsewhere), compilers (p566) sketched out.

the elaboration of John Dee's Monas as code basis through theorems

...

at the same time a question of mechanism relates to Sadean life coding. model/description of a process again.

(after SICP computer science as involved solely in the discipline of constructing appropriate descriptive languages)

and

quotation in the interior.

and a process.

Dream Scheme interpreter: (2006.12.31:1 tech_notes#330 research#124 lisp#2)

in x86 assembly

http://www.stripedgazelle.org/joey/dream.html

note:

The design for the 'dream' Scheme interpreter began with the design given in Abelson and Sussman's Structure and Interpretation of Computer Programs.

also:

SIOD porting

Explicit-Control Evaluator (2006.12.30:3 tech_notes#329 research#123 lispcpu#5 lisp#1)

again, chapter five of SICP:

from: http://www.ida.liu.se/~tobnu/scheme2llvm/

This is a small (about 1K lines) self applicable scheme toy compiler which compiles to C-code, and a version that compiles to LLVM with the types fixnum, symbols, strings, functions and vectors (cons cells are seen as vectors of size 2).

and:

The code is quite similar to the code in SICP (Structure and Interpretation of Computer Programs), chapter five, with the difference that it implements the extra functionality that SICP assumes that the explicit control evaluator (virtual machine) already have. Much functionality of the compiler is implemented in a subset of scheme, c-defines (llvm-defines), which are compiled to C-functions (llvm functions).

code for SICP at:

http://mitpress.mit.edu/sicp/code/index.html

quotation and exteriority: (2006.12.30:2 research#122 instructionsets_additions#2)

quotation in the interior

quotation standing as existent

and from:

http://tunes.org/HLL/meta/quotation.html

we have:

So that we manipulate programs written in a language from another language (possibly the same), the meta-language, we need an embedding of base-level source as data for the meta-level system. This embedding may be more or less flexible: it may be dynamically invoked at runtime, or only at compile-time; it may allow for wide range of manipulations, or be but an indirection level before evaluation, without any possibility to effect sensible manipulations on code. In any case, such embedding is called "quoting", and is a very important topic in reflective systems. Indeed, quoting raises the fundamental question in a reflective system: what are the limits of an object? what are the limits of the system? what is to be explicit? what is to be implicit?

// emphasis last two questions above.

and also ref in above to:

On Computational Interpretations of the Modal Logic S4

http://www.ubka.uni-karlsruhe.de/vvv/ira/1996/35/35.text

Godel (and endophysics) again - for Instruction Sets updating/crystalpunk january bonanza (2006.12.30:1 research#121 instructionsets_additions#1)

The great 'eye-opener' in modern physics is Godel's mathematical discovery that there exist truths which are not accessible in a finite number of steps from within the formal system which implies them. The decisive notion is 'from within.' Godel would never have reached this result if stepping outside of the formalism had not been an option.

[Otto Roessler. Endophysics p. 120. In relation to nowness as a Godel boundary]

at the same time potential structure examination (video) of black box hackery a la 23c3 congress

research notes/todo: (2006.12.29:3 research#120 tech_notes#328)

[also within alice/kodiak.lisp representation import/export of worlds]

also as performative expansion of xxxxx_at_interface

on the one hand, now that which we can call alice, the environment based on the existent (GNU Emacs and beyond)

on the other hand the existent cpu or hardware (either as fpga or using the ATMega (see cpu link)

environment and series of (preferably networked, interpretative, bit spouting) CPUs within the black marias cpu_model connected by way of serial (and thus USB, or Ethernet using the ENC28J60 from Microchip)

also interface to paper circuits.

Film before Film: What Really Happened Between the Images? (1986) by Werner Nekes

(position of Edison and Black Maria studio within such a history)

Universal Dovetailer. Generation of FPGA HDL. Language generation.

Code stepper.

import/export of both evaluatable code and code environments. OSC.

continuations. leakage. representation (our language finally).

Last chapter of SICP: (2006.12.29:2 lispcpu#4 research#119 tech_notes#327)

Chapter 5: Computing with Register Machines

walking through a Scheme interpreter and compiler for hypothetical (simulated in this instance) stack-based register machine (minus (as simulated in Scheme) various primitive operations such as car, cons))

for such primitives (and a similar implementation) also see:

http://www.frank-buss.de/lispcpu/lispcpu.lisp.txt

(defconstant primitives '#(+ - < > <= >= /= = * set quote setq defun progn get-time set-time set-led get-led while cons car cdr if))

Storage of car, cdr structures is outlined in section 5.3 p533. also garbage collection

towards lispcpu, also perhaps ATMega interpreter/compiler .#xxxxx two sides/faces

to promiscuOS project across range of instances:

ref: http://download.plt-scheme.org/mzscheme/mz-103p1-bin-i386-kernel-tgz.html

possibly also expressed as:

http://fresh.homeunix.net/~luke/shbuf/

[look into further for processes and networking in Emacs Lisp using Distel: http://fresh.homeunix.net/~luke/distel/]

where do we arrive? to specify an architecture of pipes, leaks and pools - shared, networked and promiscuous with intentional and automated data and code generation, network transport and sloughing off of neighbouring data. transparent, non-segmented memory as an option. how would this look and how far do we go in specifying the environment (see 0 above)

promiscuOS quotation: (2006.12.10:1 promiscuOS_notes#7 research#118)

/*
 * pipefs should _never_ be mounted by userland - too much of security hassle,
 * no real gain from having the whole whorehouse mounted. So we don't need
 * any operations on the root directory. However, we need a non-trivial
 * d_name - pipe: will go nicely and kill the special-casing in procfs.
 */

[from /usr/src/linux-2.6.11/fs/pipe.c]

notes/links for leaking pipes also regarding pipe.c:

http://www.linux.com/guides/lki-3.shtml

pipe_mnt = kern_mount(&pipe_fs_type);

pipe system call bridges user/kernel space:

http://db.ilug-bom.org.in/Documentation/lpg/node11.html

pipe buffers:

http://lwn.net/Articles/119682/

and some tee():

http://lwn.net/Articles/179434/

random promiscuOS notes:

Python - twisted framework

serialised or pickled objects

eval/parsing

leaks - pools / code reserves

local and remote function and environment repositories. continuation inspired frozen states for import and export.

[code object]text - interfacepools and paths between pools
leaksconnection/piping

[promiscuOS + CPU work] as: (2006.12.08:2 research#117 promiscuOS_notes#6 OS#1)

an active highly practical investigation of how the CPU and Operating System, those twin (Babel) towers of abstraction, map other domains (at the same time mapping each other - the x rings of processor privelege mapped under Linux kernel to two spaces: user and kernel space) - the domain of life coding.

notes:

---> here the fpga research, the switching of circuits UNDER

instruction and paper circuits pile

twin:

user ____ kernel

Kernel/OS definitions and related ideas

The kernel or operating system abstracts that which is uniform (the hardware-tagged space of memory cells) as that which is segmented according to process (PID - unique ID) and user. Shared memory space. Clone and fork of processes in a tree structure which mimes the filesystem hierarchy.

From Daniel. P Bovet et al. Understanding the Linux Kernel. 2005. O'Reilly:

The operating system must fulfill two main objectives:

[further...]

In a multiuser system, each user has a private space on the machine; typically, he owns some quota of the disk space to store files, receives private mail messages, and so on. The operating system must ensure that the private portion of a user space is visible only to its owner. In particular, it must ensure that no user can exploit a system application for the purpose of violating the private space of another user.

[further...]

Processes

All operating systems use one fundamental abstraction: the process. A process can be defined either as "an instance of a program in execution" or as the "execution context" of a running program. In traditional operating systems, a process executes a single sequence of instructions in an address space; the address space is the set of memory addresses that the process is allowed to reference. Modern operating systems allow processes with multiple execution flows that is, multiple sequences of instructions executed in the same address space.

[further...]

Unix-like operating systems adopt a process/kernel model . Each process has the illusion that it's the only process on the machine, and it has exclusive access to the operating system services. Whenever a process makes a system call (i.e., a request to the kernel, see Chapter 10), the hardware changes the privilege mode from User Mode to Kernel Mode, and the process starts the execution of a kernel procedure with a strictly limited purpose. In this way, the operating system acts within the execution context of the process in order to satisfy its request. Whenever the request is fully satisfied, the kernel procedure forces the hardware to return to User Mode and the process continues its execution from the instruction following the system call.

[Online ref: http://linux-security.cn/ebooks/ulk3-html/0596005652/understandlk-CHP-1-SECT-4.html]

for promiscuOS... some notes:

leaks across process memory (implemented beneath the process - within generic segmentation faultcode), filesystem, sockets+pipes (referred to as IPC): memory is context. segregation of memory is seperation of user and process.

address space of a process: all linear addresses that the process is allowed to use (see p.352 Understanding)

pipes p.776+ also the pipe code we found: lp-01 which copies file descriptors (pipe is only accessible to parent process). FIFO allows for arbitrary piping and is associated with a kernel buffer.

IPC shared memory. executable in shared memory?

http://user-mode-linux.sourceforge.net/projects.html - note DSM - distributed shared memory:

This can be done with UML because UML's physical memory is really virtual memory on the host, so it can be mapped and unmapped. So, the idea is to spread a single UML instance over multiple hosts by running a virtual processor on each host and partitioning UML physical memory between them. A page that's present on one node will be unmapped from the others. If one of the other nodes accesses it, it will fault, and a new low-level fault handler will figure out what node currently has it, and request that it be sent over. The other node will unmap it, and copy it over to the requesting node, which will map it in to the appropriate location and continue running.

In UML codebase we're also looking at:

linux-2.6.19/arch/um/sys-i386/signal.c:364: force_sig(SIGSEGV, current);

also:

int handle_page_fault(unsigned long address, unsigned long ip,... in:

linux-2.6.19/arch/um/kernel/trap.c:203: force_sig_info(SIGSEGV, &si, current);

xx___

how exactly does UML work with memory management?

"A page fault exception is raised when the addressed page is not present in memory, the corresponding page table entry is null or a violation of the paging protection mechanism has occurred." [ULK]. Linux handles a page fault exception with the page fault handler "do_page_fault()". This handler can be found in "arch/i386/mm/fault.c". You may also need to read related contents of Chapter 4 in LKP "The next most important piece of the port is the virtual memory emulation. An important job of the kernel is to maintain a separate memory context for each process, making it impossible for one process to access memory belonging to another. Native kernels accomplish this by allocating physical pages and doing hardware magic to map them into the appropriate location in a process virtual memory. UML emulates this first by creating a file that is the same size as the physical memory that UML has been told it has, and then by mapping this file as a whole into an area of its virtual memory that will be treated as its "physical" memory. When a process needs memory to be allocated, pages will be allocated from this area and the corresponding pages in the file will be mmapped() into the process virtual memory.

access to file?

UML must also emulate hardware faults and device interrupts. The most important fault that needs to be emulated is a page fault, which happens whenever a process does an invalid memory access. In UML this generates a SIGSEGV; the handler does the necessary checking to see if the access is valid and a new page needs to be mapped into the process (if it's invalid, the process is sent the SIGSEGV). Device interrupts are generally emulated with SIGIO on the file descriptor used to communicate with the virtual device. The timer is implemented by requesting a SIGVTALRM timer from the host kernel. SIGSEGV, SIGIO, and SIGVTALRM are the equivalent of hardware traps. Just as processes on a physical Linux machine aren't affected by hardware traps unless the kernel converts them into Linux signals, these signals don't affect any UML processes unless the UML kernel converts them into Linux signals. UML installs its own handlers for these signals, which run in UML kernel mode." ... Jeff Dike

from: http://lass.cs.umass.edu/~shenoy/courses/spring04/577/lab5.html

raw access to filesystem (/dev/hda1 for example)

path of execution. passed down through shell.

PromiscuOS notes2: (2006.12.05:2 promiscuOS_notes#3 research#116)

1] Simple Grid Protocol (which certainly is simple) - runs on CLisp and consists of network code, querying, and eval.

/etc/services and then inetd start cpur.lisp. Tracking (server) and notify (process) maintain local list of IPs for code import/eval.

but eval doesn't give us a shared/promiscuous environment.

...for promiscuOS we need to maintain a list of local and otherwise promiscuOS'ers - exported to a central accessible list which can be downloaded regularly. zeroconf for local.

2] obvious differentiation between promiscuOS'ers and code environment of other machines/networks which equally well be probed and executed.

3] extent of VM layer if we modify kernel and strip down overlying OS

embedding 40106 invertor/Schmitt trigger:

ogg vorbis recording:

http://plot.bek.no/~crash2005/paper1_12_2006.ogg

what exactly does it mean to submit an instruction to (mute) hardware (2006.12.03:2)

a border crossing

more links for our CPU: (2006.12.03:1 cpu#1 research#113)

http://www.hanssummers.com/electronics/misc/gates/index.htm

PISC:

The Pathetic Instruction Set Computer is a model processor constructed entirely of discrete logic, illustrating the principles of both hardwired and microprogrammed CPUs. Requiring only 22 standard TTL chips (excluding memory)...

http://www.zetetics.com/bj/papers/piscedu2.htm

and a relation:

Mark 2 FORTH Computer

http://www.holmea.demon.co.uk/Mk2/Architecture.htm

and some lists of links:

http://www.holmea.demon.co.uk/Links.htm

http://www.homebrewcpu.com/links.htm

The essential unfolding of technology threatens revealing, threatens 07:38 (2006.11.29:1)

it with the possibility that all revealing will be consumed in ordering and that everything will present itself only in the unconcealment of standing-reserve. Human activity can never directly counter this danger. Human achievement alone can never banish it. But human reflection can ponder the fact that all saving power must be of a higher essence than what is endangered, though at the same time kindred to it.

[Martin Heidegger. The Question Concerning Technology]

of note for promiscuOS:: (2006.11.28:1 promiscuOS_notes#2 tech_notes#312 research#111)

SBUML is an extension to User-mode Linux(UML) that can save complete Linux runtime states in mid-execution(including all hard disks, devices, processes, and kernel space). The same state can be restored at a later time on the same PC, or migrated to another PC. The states can be delta compressed to a few megabytes or less, making it practical to download running Linux machines from websites.

http://sbuml.sourceforge.net/

Cartesian rationalism 05:50 (2006.11.25:3)

consists of a single falsifiable hypothesis: The world, which to the individual has the character of a Big Dream, may be well defined as far as the the quantitative relations between its qualitative features are concerned (hypothesis of relational consistency). The universe then would behave like a giant dynamical system ("machine"). The first major implication is determinism, while the second implication is exteriority...

The exteriority principle was invented by Descartes in the 17th century. It was elaborated by Ludwig Feuerbach in the 19th and Martin Buber and Helmut Plessner in the 20th. It was rediscovered and named by Levinas [ref. Time and the Other]. Lower level worlds (in the computer) by definition pose an ethical problem because of one's being completely exterior to them.

[Otto E. Roessler. Boscovich Covariance. Endophysics p. 103]

The forest clearing: setting for xxxxx_at_interface 05:37 (2006.11.25:2)

We call this openness that grants a possible letting-appear and show 'opening.' In the history of language the German word Lichtung is a translation derived from the French clairiere It is formed in accordance with the older words Waldung [foresting] and Feldung [fielding].

The forest clearing [or opening] is experienced in contrast to dense forest, called Dickung in our older language. The substantive Lichtung goes back to the verb lichten. The adjective licht is the same word as 'open.' To open something means to make it light, free and open, e.g., to make the forest free of trees at one place. The free space thus originating is the clearing. What is light in the sense of being free and open has nothing in common with the adjective �light� which means �bright,� neither linguistically nor factually. This is to be observed for the difference between openness and light. Still, it is possible that a factual relation between the two exists. Light can stream into the clearing, into its openness, and let brightness play with darkness in it. But light never first creates openness. Rather, light presupposes openness. However, the clearing, the open region, is not only free for brightness and darkness but also for resonance and echo, for sound and the diminishing of sound. The clearing is the open region for everything that becomes present and absent.

[Martin Heidegger.The End of Philosophy and the Task of Thinking. Routledge p.441]

He wanted... 05:26 (2006.11.25:1)

a modification worked into one rocket, only one. Its serial number had been removed, and five zeroes painted in.

[Thomas Pynchon. Gravity's Rainbow p. 431 Picador]

mobile code links: 23:23 (2006.11.19:1 research#107 tech_notes#310)

by way of http://bc.tech.coop/blog/061119.html

mosref running with mosquito-lisp

mobile code platform 03:48 (2006.11.18:1 research#106 tech_notes#309)

TODO for data_radio project and also promiscuOS

also to note:

http://en.wikipedia.org/wiki/WASTE

and (for promiscuOS): http://www.vanheusden.com/listenpipe/

Listenpipe can be used to sit between 2 applications that are interfaced with pipes. It will pass through data as is but also store what is send/received in a logfile as well.

for leaking pipe code

LispOS links 07:22 (2006.11.16:3 tech_notes#308 research#105)

by way of:

http://bc.tech.coop/blog/061115.html

MzScheme on OSKit: http://download.plt-scheme.org/mzscheme/mz-103p1-bin-i386-kernel-tgz.html

Emacs standing alone on a Linux Kernel: http://www.informatimago.com/linux/emacs-on-user-mode-linux.html

some possible uses for promiscuOS

copper tape transparency noise circuit 03:29 (2006.11.16:1 research#104 tech_notes#307)

first prototype:

03:11 (2006.11.13:2)

The great 'eye-opener' in modern physics is Godel's mathematical discovery that there exist truths which are not accessible in a finite number of steps from within the formal system which implies them. The decisive notion is 'from within.' Godel would bever have reached this result if stepping outside of the formalism had not been an option.

[Otto Roessler. Endophysics p. 120. In relation to nowness as a Godel boundary]

FPGA bitstream to Flash to start on power-up: 11:12 (2006.10.31:1 fpga#22 tech_notes#300 research#102)

In theory:

1] export XILINX=~/Xilinx // where we have our Xilinx distribution

2] ~/Xilinx/bin/lin/promgen -u 0 ~/piksel/fpga_src/tutorail2/tutorial.bit -p exo -s 2048 // make EXO file from our VGA project bitfile

3] xsload -b xsa-50 -flash ~/piksel/fpga_src/tutorail2/tutorial.exo // downloads to the board

to test the last step:...

TESTED on T20 (though strangely xstest fails)

[ see further: http://www.xess.com/manuals/xstools-v4_0.pdf ]

Progressive zoom out from the black CPU (lens zoom visible or tracking 11:08 (2006.10.24:1 research#101 interface_and_society_notes#5)

obviously still within the black maria film studio which is itself within the forest):

Zoom out follows a trajectory from:

a) CPU interior. - Salo opening bibliography

b) CPU pin outs/data sheet - interface

c) CPU exterior within/at centre of the film studio (as in framed image below)

d) Salo + Welt am Draht KOPF quotation transitions

also note our own MICRO-ASSEMBLER and compression-technology-led permuted films

From: 18:08 (2006.10.23:2 research#100 interface_and_society_notes#4)

W.K.L and Antonia Dickson: History of the Kinetograph (facsimile 2000 MOMA NYC):

p20: regarding the Kinetographic theatre or black maria:

[quote]

As we peer into the illusive depths we seem transported to one of those cheerful banqueting halls of old, where the feudal chief made merry with human terrors, draping the walls with portentious black, and thoughtfully providing a set of coffins for the accommodation of his guests. And what is this mysterious cell at the other extremity, sharply outlined against the dazzling radiance of the middle ground and steeped in an angry crimson hue? Are these inquisatorial dungeons, and is that lurid glare the advance guard of the awful Question? Is that gentle persuasive in process of administration, and do these half-guessed recesses conceal the hellish paraphernalia of rack and screw, glowing iron and crushed stone? Has the doom of ages overtaken our wizard at last, and is he expiating, with twisted limb and scorching flesh, the treasures of his unlawful wisdom? Ah, me! that the prosaic truth must be told. No dungeons are these, thrilling with awful possibilities, but simply a building for the better "taking" of kinetographic subjects.

xx___ 17:51 (2006.10.23:1 research#99 interface_and_society_notes#3)

The CPU is a highly interiorised existent device/structure in the world. The interior is unknown - interface is presented both by way of assigned pins (labelled by numbers/assignments and control, I/O or time driven functions) and the literature on construct of the data sheet which presents this annotation - to some degree often incorporating purely theoretical rather than practical information. The product unknown to the manufacturer returns conjecture. There is a relation to measurement and exploration by way of reverse engineering.

[CPU image. the black box. data sheet Zilog Z80. machinery of reverse engineering]

To extrapolate from such a (fictional) view of the CPU (in the world) towards the world/existent (and thus the arena of life coding: the darkened theatre and its double) implies an interiority which is rationality (a machine) with pin-outs extending deep into the black forest of an outside. It's a necessary exchange - expansion of CPU/machine interiority implies a sadistic or cruel rationality (contained) of the machinic. The CPU is (always) a rabbit hole within this forest which accommodates another extrapolated CPU - Edison's Black Maria. A film studio with a constrained or reduced instruction set which well allows for viral reproduction and thus execution. This studio, in the forest, precisely mimes interiority. The encoding of the instruction set permutation, the program, which equally implies circular motion by way of both vertical sprocket-led motion (reproduction) and a horizontal rotation of the studio itself repeating the world's motion in attempting to track the light of the sun, a telescope's motion; this encoding is equally used within the first hardwired CPU of Konrad Zuse - a hardwired arithmetic unit implying circuit selection parallels the permutational (editing) possibilities of that life coding demonstrative double which is cinema.

ref also:

http://irb.cs.tu-berlin.de/~zuse/Konrad_Zuse/Neumann_vs_Zuse.html

John von Neumann's Computer Concepts versus Konrad Zuse's Ideas and the Machines Z1 and Z3

[Klossowski image/Salo bibliography-ending wrapped in as image and text. Black Maria interior shot. shot. Edison text p. 20+ Dickson's history transcribed below]

Extrapolating further on this tracking (out) trajectory from CPU to Black Maria studio (a mobile police cell) to world/existent and maintaining a relation to containment (prison of language and rationalism), leads both to a permutational filmic construct arrived at when film, like all software, turns in on itself, eats its own promiscuous tail, in compiling or interpreting harmless, passive data as world-active code - an everyday operation which allows for an interface between high level expressive language (comments are nevertheless discarded) and the machinic: machine code exactly as it is termed.

[?. an interpreter in hardware - Lisp transcription]

This film: Rainer Werner Fassbinder's Welt am Draht. Thus a series of ever expanding containers, Searle's Chinese room embeddings. leading both to the Kopf embeddings within Fassbinder's two part magnum opus, and equally to the question of interface. The clue that such a world reverse engineering, this mock turtle science, is on the right paranoiac or conspiratorial track revealed through further empirical evidence or coincidence. Fassbinder's Welt Am Draht (describe) is based on a novel, Simulacron-3, by Daniel F. Galouye in 1964, which is well referenced at the beginning of Otto Roessler's first manifesto for a new kind of science: Endophysics (1992) , or precisely science or physics from WITHIN. Equally the question of a "world as interface" - a thought movement made possible by the use of computers and the descriptive active means of programming languages to model the wonderland world: embedding a world for an equally embeddable observer (the Kopf). A science born of a science fiction which further following the conspiratorial track is further related (in 1970) by Konrad Zuse in his essay Rechnende Raum, or Calculating space/room. The circuit is complete but the question remains of observer interiority - access to a falsified data sheet for a cruel world or rabbit hole CPU. [expand on Endophysics and the observer]

[Welt am Draht images. Tower of Babel and Breugel CPU]

FPGA/VHDL/Lisp 16:24 (2006.10.20:1 fpga#21 research#98 tech_notes#295)

http://www.cs.utexas.edu/users/moore/acl2/v3-0/distrib/acl2-sources/books/workshops/1999/vhdl/

quote:

This directory contains the supporting files for Chapter 11, "Using Macros to Mimic VHDL", by Dominique Borrione, Philippe Georgelin, and Vanderlei Rodrigues, in "Computer-Aided Reasoning: ACL2 Case Studies", edited by M. Kaufmann, P. Manolios, J Moore (Kluwer, 2000, p.167-182).

and:

File fact.lisp is the example in Figure 1. It is the description of the circuit that computes the factorial function, using two concurrent processes. It uses the macros defined in the preceding file.

Brief post-xxxxx_at_piksel notes: 13:19 (2006.10.19:2 xxxxx_at_piksel_notes#48 interface_and_society_notes#2 research#97)

1] Slide 0: All hardware is necessarily closed, black boxed - another exposure (potentially falsified) by way of the data sheet enumerating instruction set, pin outs and exposed physical characteristics. A potential for reverse engineering of CPU, black box, brain or world (that process outlined).

2] From day one:

a) Reversibility, Augustine, Poincare', Friedkin

b) Tragedy and arithmetic.

c) Rationalism and the container/frame (an interiority: incompleteness, inside - first person). By way of endophysics (inside) an investigation of computer science and interiority: that computational technologies (hardware and software) enable a new thinking of the interior (enabling the science of endophysics). Thus:

(computer) hardware as a theatre of interiority along the hard/soft line of execution

d) Economies: a white rabbit economy within the CPU (for Oslo also below). The transfromation from notebook to white rabbit as computationally too expensive in terms of complexity and thus entropy. Equally an entropic world economy as outlined within Kekule'/Pynchon quote.

refs: Anaxagoras fragments, Leibniz-Clarke correspondence

e) xxxxx defined now as the active construction of a non-subject space (paradise) through noise

3] Towards Oslo: specification of a CPU:

a) Edison black maria(h) exterior CPU model. (The instruction set is cinema). Interior stills (Salo stills, exposure). Model and flattened studio. Revolving studio platform and sun opening (a hole).

b) JDM. John Dee Machines - monadic CPU, autumnal CPU (rabbit holes moss and web covered, forest, mushrooms).

sleep CPU instruction (kill cell). time machine and Alice functions. autumnal pinouts (I/O leaf indication), contained experience and sample lige coding manual for machinery...

sources:

Pieter Breugel the Elder: Tower of Babel, Allegory of Autumn (the younger?), Flemish Proverbs

FPGA/artistic CPU development: 20:51 (2006.10.10:1 research#96 xxxxx_at_piksel_notes#47 fpga#19)

our components and architecture: Alice in Wonderland, the framed NAND, a mushroom (cloud) spacing, the grid with bottom right hand corner mark shifted up and right, seasonal software and CPU, also morning, afternoon, evening and night sections accessible, Salo circles of hell, Bruegel proverb fragment, quotation,

circular memory and Atrocity exhibition instruction set.

off with her head instruction

from below also:

a) Large Glass - Duchamp. A mechanism (in space).

b) The boudoir/bedroom. A singular eye.

c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.

d) Doubling/ghosting of gates - twinned Alice CPU (also theatre and its double CPU)

NAND notes: 14:03 (2006.10.05:3 tech_notes#290 xxxxx_at_piksel_notes#46 research#95)

the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.

it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.

http://www.play-hookey.com/digital/rs_nand_latch.html again

Brief note: There is No Software (Friedrich Kittler): 20:49 (2006.10.04:3 research#94 xxxxx_at_piksel_notes#45)

[quote]

This all-important property of being programmable has, in all evidence, nothing to do with software; it is an exclusive feature of hardware, more or less suited as it is to house some notation system. When Claude Shannon, in 1937, proved in what is probably the most consequential MA thesis ever written that simple telegraph switching relays can implement by means of their different interconnections the whole of Boolean algebra, such a physical notation system was established.

When meanings come down to sentences, sentences to words, and words to letters, there is no software at all. Rather, there would be no software if computer systems were not surrounded any longer by an environment of everyday languages.

notes today (in conversation with Eva Verhoeven): 19:55 (2006.10.04:2 research#93 xxxxx_at_piksel_notes#44)

1] flip-flop time machine

(first ref in search offers:

http://www-personal.umich.edu/~reginald/timemchn.html

)

2] Alice in Wonderland CPU mechanisms - instruction set also with reference to symmetry which could be across CPU components/multiple CPUs - Alice is itself the communication mechanism (off with her head as propogated instruction). symmetry of the NAND gates in the S/R flipflop - also ahead of itself in time-machine reference above.

time-machine/Alice CPU of chained cells and gates. instruction futures

[further notes on Steele and Sussman's LispCPU]

1] Microcode:

quote [p35]:

Each of the two parts, EVAL and GC, is itself divided into two parts: registers and controller. The registers provide storage for type/pointer words, and are connected by a common bus in each part. Each controller is a finite-state machine implemented as a PLA, plus some random logic. Each PLA is organised as a micro-code ROM, addressed by a "Micro-PC" and yielding a set of control signals, including register controls and a new micro_PC indicating the next state.

signals enumerated on p36

p39. [SIMPLE Microcode] There are five kinds of operation EVAL can request from the GC (which give EVAL the step-eval signal to advance):

NOP, CAR/CDR, CONS/NCONS, RPLACD and load/store Q (one of GC's registers).

p40:

[quote]

The CONS operation accepts a car pointer from the E bus, takes the contents of Q to be the cdr pointer and then allocates a new two-word cell containing the car and cdr. A pointer to the result, with type 0 (list) is left in Q.

The Microcoded PLA is produced by software from the assembly listing (p48+) produced by the micro-assembler software from the listing (p43+)

2] The register cell

[p63]

One-bit register cell. The signal LD during O/1 loads the cell from the data bus. The signal RD during O/1 drives the bus from the cell. The cell is refreshed during O/2.

FPGA practice mimes 22:32 (2006.10.03:5 fpga#15 tech_notes#286 research#91 xxxxx_at_piksel_notes#42)

the high- low- level overlap we are interested in

in terms of a methodology of description (code, the diagram, a description of behaviour, software generation of HDL)

Lisp CPU (cell) structure - ie. representation - in the CPU: 21:19 (2006.10.03:4 tech_notes#285 fpga#14 lispcpu#2 research#90 xxxxx_at_piksel_notes#41)

after: Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode

Guy Steele and Gerald Sussman

(http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT

see:

1] Architecture reflectes language structure

2] The overlap of high level and machine language is also dictated by necessity to manipulate program as data

3] Programs are represented as nested Lisp data structures -> as a tree of linked records subject to a recursive tree walk

4] Lists are represented by records each of which contains 2 pointers to other records - car and cdr

5] The type field associated with each pointer is used to encode opcodes and return addresses

6] p17 implementation:

7] Two consecutive words of memory hold a list cell - each word can hold a type field and an address field (an address referenced within linear memory)

8] The evaluator and the storage manager as individual processors each with a state machine controller and a set of registers

contents of any register is address field and type field

9] p32 evaluation and procedure call (type 6):

We have a 3-bit type field which provides 8 opcodes (recall 7 as quotation) - address part of a word has different function depending on type (6 is procedure call).

quote:

The evaluation of type 4 (procedure) results in a pointer to the newly allocated word pair. This pointer has type 3 (closure). The car of the pair contains the cdr of the procedure: this is the code body of the procedure. The cdr of the pair contains the current environment.

and:

A procedure call (type 6) is the most complicated... It is a list of indefinite length, chained together by cdr pointers. Each cdr pointer except the last MUST have type 0 (list). The last cdr pointer should have a zero address and a non-ZERO type. This last type specifies the operation to be performed. In CDRing down the list, SIMPLE evaluates each of the expressions in the car, saving the resulting values. These values are available as arguments to the operation to be performed.

operations in tyoe here such as car, cdr, cons, atom, progn, list and funcall

10] further question of recursion in hardware by way of closures:

A closure combines the code of a function with a special lexical environment bound to that function (scope).

sync and VGA fine 20:05 (2006.10.03:2 tech_notes#283 research#89)

using FPGA for H and V sync

(for RGB from Schmitt triggers remember to link GND from board(s) to box)

For FPGA expansion (XST-3.0 board and XSA-50): 21:15 (2006.10.02:2 tech_notes#281 research#88 fpga#11)

FPGA Pins:

Hsync: 85 out

Vsync: 86 out

Input: Output: all bi-directional

0: 67 12

1: 39 13

2: 44 19

3: 46 20

4: 49 21

5: 57 22

6: 60 23

7: 62 26

notes: 11:18 (2006.10.02:1 research#87 tech_notes#280)

1] Salo (or any other film) modelled as/in Lisp process with a necessary overlap of (changed) language, structure and quotation - active language ie. that we do not simply slot the events of the film into an established framework but rather map the processes as/and characters.

2]. FPGA extension board tests (+5v) + VGA (need more headers). also test chess matrix interface. PCB photoboards. Daniel Paul Schreber. Notes...

3] Lisp cell structure to expand on. in the CPU/FPGA. a symbol

4] To collate the instruction set and the fictional data sheet with addition now of Alice instructions - Alice data bus or transmission lines ( And after that other voices went on (What a number of people there are in the carriage!' thought Alice), saying, `She must go by post, as she's got a head on her -- ' `She must be sent as a message by the telegraph -- ' )...

instructions such as "off with her head" stack head. Salo quotation cells

Expanded from xxxxx_at_piksel release text: 17:36 (2006.09.27:1 research#86 xxxxx_at_piksel_notes#40)

After Artaud, the CPU (central processing unit) and its double mimes The Theatre and its Double. On the one hand, there is the System or entropic operation of a necessarily cynical machine for living, an atrocity exhibition, on the other hand the specification of an artistic CPU for life coding.

The CPU is the black boxed (after Edison's black mariah studio) theatre where the action takes place (also to expand further the limbs of that primal studio as our pinouts and some kind of internal sunlight, through the roof is there in the darkness - we can see all operations there; cats dancing, emotions). The script is performed and to some extent improvised (compiler and interpreter). Symbolic manipulation (implicating representation - mathematics) takes precedence; although the ALU (Arithmetic Logic Unit) takes up a good deal of space within the contemporary theatre, the script (instruction set driven) makes little reference to these props - indeed in unconventional existent designs (such as the Lisp CPU) the ALU is completely discarded.

fictional data sheet and then a specification of components (circuit diagram) 19:56 (2006.09.26:1 research#85 xxxxx_at_piksel_notes#39)

Breughel fragment (after a proverb) and mushroom (cloud)

encompassing cynicism, simulation and personal description. circles of hell. clock cycles - 24fps to 24 Hz. from below what such components could comprise - a circuit diagram. assembled pin outs and data sheets (eg. instruction sets). drafting after "the existent," and obviously existent data sheet format:

For logic eg. 4093 2-Input NAND Schmitt trigger:

Title

General Description

Features

Applications

Connection diagram

Absolute maximum ratings, Recommended operating conditions and DC electrical characteristics

Typical applications [circuit diagrams]

Typical performance characteristics [graph]

Input and output characteristics

AC test circuits and switching time waveforms

Physical dimensions (packaging)

and for Z80:

Z8400 Z80 CPU Central Processing Unit

Zilog Product Specification

FEATURES

GENERAL DESCRIPTION [+ block diagram]

Z80 MICROPROCESSOR FAMILY

Z80 CPU REGISTERS [+several figures and tables]

INTERRUPTS: GENERAL OPERATION

INSTRUCTION SET [divided as to groups, inc. summary of flag operations and symbolic notation appendices]

PIN DESCRIPTIONS

CPU TIMING [more diagrams for opcode fetch, memory read and write and so on]

AC CHARACTERISTICS

ORDERING INFORMATION

Further:

This can be specified as the data sheet[s]. The simulation is imaginary code running on this hardware - based perhaps on the simulations code within SICP outlined somewhere here:

3.3.4 - http://mitpress.mit.edu/sicp/full-text/book/book-Z-H-22.html#%_sec_3.3.4

quote:

Representing wires

A wire in our simulation will be a computational object with two local state variables: a signal-value (initially taken to be 0) and a collection of action-procedures to be run when the signal changes value. We implement the wire, using message-passing style, as a collection of local procedures together with a dispatch procedure that selects the appropriate local operation, just as we did with the simple bank-account object in section 3.1.1:

(define (make-wire)
  (let ((signal-value 0) (action-procedures '()))
    (define (set-my-signal! new-value)
      (if (not (= signal-value new-value))
          (begin (set! signal-value new-value)
                 (call-each action-procedures))
          'done))
    (define (accept-action-procedure! proc)
      (set! action-procedures (cons proc action-procedures))
      (proc))
    (define (dispatch m)
      (cond ((eq? m 'get-signal) signal-value)
            ((eq? m 'set-signal!) set-my-signal!)
            ((eq? m 'add-action!) accept-action-procedure!)
            (else (error "Unknown operation -- WIRE" m))))
    dispatch))

;; The local procedure set-my-signal! tests whether the new signal
;; value changes the signal on the wire. If so, it runs each of the
;; action procedures, using the following procedure call-each, which
;; calls each of the items in a list of no-argument procedures:

(define (call-each procedures)
  (if (null? procedures)
      'done
      (begin
        ((car procedures))
        (call-each (cdr procedures)))))

How speculative, open hardware can operate, be imagined along an 13:36 (2006.09.25:1 research#84 xxxxx_at_piksel_notes#38)

expressive line of (to be exposed) functionality - a reasoning in the evident, the means of description (software) and the EXISTENT.

random: 19:54 (2006.09.20:2 tech_notes#278 research#83 xxxxx_at_piksel_notes#37)

1) J.G Ballard's Atrocity Exhibition as closest to an (expanded, to some extent architectural) instruction set for an imaginary CPU.

yet to be codified

2) circular memory (bubble is similar).

Z80 17:50 (2006.09.20:1 tech_notes#277 research#82 xxxxx_at_piksel_notes#36)

(to test IOE expansion board)

Of interest here is the ghosting of registers:

There are two sets of six general purpose registers + accumulator and flag registers (duplicate set swopped (values exchanged) by the Exchange instruction) - "The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response."

(From Z80 product specification).

Further 16 -bit wide registers for index, stack pointer,program counter and split (down to 8-bit) interrupt and memory reset. Also interrupt and other flip-flops.

Instruction set:

divided into categories, and described as to mnemonics and opcode

also addressing mode

LD r,r'

EX DE,HL

INC r

NEG

NOP

ADD HL, ss

RLC r

BIT b, r

JP nn

CALL nn

IN A, (n)

see also: http://www.z80.info/#BASICS_INST

also:

Binary form of opcodes
   
  Example:   LD r,r'
 
the 8-bit binary opcode is
 
     01dddsss
 
   ...where "ddd" is a three-bit field specifying the destination,
  and "sss" is a three-bit field specifying the source.
 
is shown below as
                          r   r'
                      01 xxx xxx
 

overmapping Salo/Sadean life coding onto instruction sets

in the first instance (or with Alice/Looking Glass/Ripper whole codified mapping - to commence in process).

to start by way of circles as registers: circle of manias, circle of shit, circle of blood (with Pasolini borrowing from Dante's nine circles of hell).

Dissect the Z80 instruction set and re-map 20:36 (2006.09.19:3 research#81)

The CPU and its double: 14:24 (2006.09.16:4 xxxxx_at_piksel_notes#34 research#80)

after Artaud - the CPU of cruelty:

Of relevance:

1] TECHNIQUE

It is a question then of making the theater, in the proper sense of the word, a function; something as localized and as precise as the circulation of the blood in the arteries...

2] THE LANGUAGE OF THE STAGE:

Meanwhile new means of recording this language must be found, whether these means belong to musical transcription or to some kind of code...

As for ordinary objects, or even the human body, raised to the dignity of signs, it is evident that one can draw one's inspiration from hieroglyphic characters, not only in order to record these signs in a readable fashion which permits them to be reproduced at will, but in order to compose on the stage precise and immediately readable symbols.

On the other hand, this code language and musical trans-cription will be valuable as a means of transcribing voices.

3] THE STAGE -- THE AUDITORIUM:

We abolish the stage and the auditorium and replace them by a single site, without partition or barrier of any kind, which will become the theater of the action.

4] THE INTERPRETATION: The spectacle will be calculated from one end to the other, like a code (un langage). Thus there will be no lost movements, all movements will obey a rhythm; and each character being merely a type, his gesticulation, physiognomy, and costume will appear like so many rays of light.

and within THE PROGRAM:

  1. A Tale by the Marquis de Sade, in which the eroticism will be transposed, allegorically mounted and figured, to create a violent exteriorization of cruelty, and a dissimulation of the remainder.

allegorically mounted within gthe CPU

Also with regard to the D flip-flop: 13:10 (2006.09.16:3 tech_notes#273 fpga#9 research#79 xxxxx_at_piksel_notes#33)

Its expansion into an 8 bit register (8 simultaneously clocked flip-flops)

or, a 4-bit shift register (data is passed along the chain)

or, a 4 bit counter

Ideas/questions: 13:00 (2006.09.16:2 tech_notes#272 fpga#8 research#78 xxxxx_at_piksel_notes#32)

1] Can we directly wire analogue signal across the FPGA (say from I/O pin to VGA resistors/input)?:

Using wires and assign. To test.

2] Limiting and/or isolation. All voltages < 3.3v

3] 8 bit to 8 bit - 8 cells or 8x8 matrix of cells. life, cellular automata - that matrix.

Replicated cells composed of micro-structures below:

4] Structures and/or instructions for the CPU:

a) Large Glass - Duchamp. A mechanism (in space).

b) The boudoir/bedroom. A singular eye.

c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.

d) Doubling/ghosting of gates - twinned Alice CPU

e) Further: a passage, quotation, representation. observer embedded

5] Gate diagrams (NOT, AND, NAND, OR, NOR) as artefacts:

6] Gate as switch. see diagrams for transistor multiplex switch symbol in a circle.

Switching across our non-optimal models.

Elaboration of physical circuits (for playing) alongside FPGA - headers and pin extension, break out. Coincident also with software (Lisp) simulation. Machine describing itself, its own coincident layers of active voltage. Reference SICP:

A Simulator for Digital Circuits:

http://mitpress.mit.edu/sicp/full-text/sicp/book/node64.html

and streams: http://mitpress.mit.edu/sicp/full-text/sicp/book/node72.html

7] S/R set-reset flip-flop:

for HDL see: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff

D. flip-flop:

Both based on the NAND gate - a principle of exclusion of the twin (the equivalent/identical binary pair - two ones). Thus of difference enabling a memory. Memory in an active circuit dependent always on current flow. In D flip-flop the clock line straddles the doubled NAND, with a replication of the signal enabling the difference.

Two snakes bite each others tails.

overlaying of high and low level possible means of description 02:22 (2006.09.15:2 research#77 xxxxx_at_piksel_notes#31)

thus FPGA as hardware simulation/black box. lacks transparency in making available (in one direction only) such parallel means. software trick. from here to Lisp language as high level machine code in directly mapping onto lispcpu

Duchamp CPU/FPGA (large glass as model) 02:18 (2006.09.15:1 research#76 xxxxx_at_piksel_notes#30)

also mushroom cloud transparency/glass component (from xxxxx cover) defined within the dual CPU schematic

from here towards the artistic instruction set (Rechnender Raum)

thematics - pursuing for FPGA internals as/is only a representation 17:22 (2006.09.14:9 tech_notes#269 research#75 xxxxx_at_piksel_notes#29)

ultimate black box:

dual CPUs ghosted...

as per waves and xxxxx_at_piksel:

After Artaud, the CPU (central processing unit) and its double mimes The Theatre and its Double. On the one hand, there is the System or entropic operation of a necessarily cynical machine for living, an atrocity exhibition, on the other hand the specification of an artistic CPU for life coding.

This is precisely the twinned instruction set we need to devise for multiple CPUs exposed as our 8 bits (one/zero), our pulses for an architecture which is somehow composed from diagrams.

Brief notes on Konrad Zuse's Calculating Space 1970 16:09 (2006.09.14:8)

(MIT TECH translation of Rechnender Raum 1969)

1) p12. "Pulses themselves have a digital character, for they are normalised in intensity and duration; they are therefore digital but their density (the number of pulses per unit time) can have any number of intermediate values, and it is therefore analogue in character. A commonly-held opinion is that the human nervous system operates on this principle."

2) p28. "In the model of modern mechanics the errors are real; in the computational model everything is strictly predetermined, not in the sense of classical mechanics but in the sense of defined calculating inputs, which can only approach the classical model. Both result in an increase in entropy.

"The initially equivalent result i.e., the increase in entropy) arises in both cases from the slight deviations from classical mechanics. In modern physical models, these deviations are defined by probablity laws; in the case of computer models through defined calculation errors."

3) diagrams - p61. Figure 30 - "... the block diagram for a calculating space... "

see diagrams for these - also Lisp CPU scans.

4) "... processes which can be characterised (at least to some extent) as a 'miscalculation' of calculating space."

5) p69. Information capacity/content is log2(n) (logarithm to the base two):

exponent/log = result b to base (number) x
gi
log5(25) = 2 =  5 power of 2 = 25
log8(2) = 3 = 3 bits for 8 possibilities

6) p71. States expressed as trees. (see also Lisp CPU).

7) p82. Reversibility and computation. OR as for example irreversible.

piksel_fpga: 12:43 (2006.09.14:1 tech_notes#267 research#73 xxxxx_at_piksel_notes#28 fpga#5)

concurrent exposed communicative (promiscuous) (instruction?) modules

exposed by way of PWM or rather single bits which can then be output as audio or as video / composite (with sync generation in software - we have an NTSC example but colour PAL is more complex - also using small resistor ladder to output) or VGA (we have vgahdl example code which looks quite simple)

FPGA as parallel CPUs 19:23 (2006.09.13:2 xxxxx_at_piksel_notes#27 research#72 tech_notes#265 fpga#4)

multiplexed internals, and only internals data access. shared or no registers - how to specify such a design...

Visually:

1] That we can draw components and connect them within a schematic entry which ranges across low and high level (black-boxed) components both from a common library and generated from our own code (using the Create Schematic Symbol entry under Design Utilities in Process).

We can access such created components under the filepath in Categories in the schematic editor when we create say a new overarching design which specifies the connection of large-scale modules/components.

2] That we can (when we select new source) choose further modules from the IP (Coregen & Architecture Wizard) option - this are classified as to various categories, including DSP, math functions, memories, and basic elements such as counters and multiplexors.

3] At the same time using the View/Edit Placed Design (Floorplanner) (under Processes: Implement, Place and Route) we can see how the logic circuitry and I/O are assigned to the CLBs (configurable logic blocks).

From the Floorplanner toolbar we can toggle ratsnest (connection) display and zoom in and out.

Macro and micro views:

Successfully modified basic CPU code from: 17:29 (2006.09.13:1 research#71 tech_notes#264 xxxxx_at_piksel_notes#26 fpga#3)

http://www.frank-buss.de/lispcpu/index.html

which defines in Verilog output (pins) RAM (on the FPGA), program counter, registers and very basic evaluator (which evaluates hard-coded instructions) - the output in this instance is to slowly flash one LED! This example demonstrates I/O pin assignment

further SDRAM:

http://www.xess.com/appnotes/an-071205-xsasdramcntl.html

Describes/implements/wraps up an SDRAM controller core.

audio:

In the instance of audio perhaps rather than dealing with the on-board audio codec of the XSTend borad, perhaps we should make use of raw 8 bit I/O from prototype area (to primitive soundcard or schmitt trigger box) - prototype area can be connected to adjacent J4 which accesses all the prototype pins from the XSA-50 header (we can look this up in the manual for assignment).

and video:

We can use VGA (some cores/sample projects - note that a useful experiment would be to send voltages (0->0.7v) for RGB signals raw to monitor... or we can use video out on XSTend board, or just resistor ladder from XSA-50 data pins as suggested in ntsc example on:

http://www.xess.com/ho03000.html

where we find all project examples.

a) re-evaluate basic workflow (for XESS boards, say counter code 18:45 (2006.09.12:1 research#70 tech_notes#263 xxxxx_at_piksel#2 fpga#2)

and I/O)

Boards used:

XSA-50 development board (Xilinx XC2S50 FPGA (Spartan II/2), 128K Flash memory for FPGA bitstream, 8 Megabyte DRAM).

and XSTend board V3.0 (XST-3.0) from XESS

(stereo codec, dual channel analogue I/O, video decoder, ethernet, usb, rs-232, ide)

see:

http://stewks.ece.stevens-tech.edu/CpE487-S05/HomeworkF04/:/hlisiteB/NotesForXessBoard.html

... example code is in VHDL.

see also free_fpga_guide for some background and install of Xstools from XESS:

link: Xstools RPM: http://www1.cs.columbia.edu/~sedwards/software/xstools-4.0.3-1.i386.rpm

x____

stages:

0] Re-install WebPack (this version 8.2.02i) from Xilinx:

http://www.xilinx.com/webpack/

1) using web-based installer which is a very lengthy process.

2) then we use the opening lines from the shell script at:

http://panteltje.com/panteltje/fpga/index.html

(which outlines solely commandline use of Xilinx toolset.)

mkdir /usr/local/lib/xilinx/
cp ~/Xilinx/bin/lin/*.so /usr/local/lib/xilinx/
echo /usr/local/lib/xilinx >> /etc/ld.so.conf
ldconfig 

and:

export XILINX=/root/Xilinx

then we can run bin/lin/xst commandline program

for full GUI:

bin/lin/ise

1] connect parallel port. start laptop. power up XSA-50 board. launch xstest from commandline to test:

xstest -b xsa-50

launch WebPack (command: Xilinx/bin/lin/ise)

2] create new project (here we define the device and the design flow)

Over the above tutorial and past work there is now a new project wizard - we skip over behaviourals and ports:

we create leddec (LED decoder as per tutorial)

3] insert VHDL module (describe/enter (in) VHDL code)

Double click on leddec in sources and edit templated source code.

4] synthesize - highlight module filename .vhd

Click on Synthesize-XST in Processes. Successful

5] implement design process eg. place and route

Highlight and then select Implement Design in Processes

6] new source - implementation constraints (I/O pins assigned as below). then Create Timing Constraints, then port tag:

Select leddec in Sources, right click and select New source following the example names as leddec_ucf, associate this with leddec and then expand User Constraints item in processes to access Create Timing Constraints - once there (new window opened for constraints editor) we can select the Ports tab to access port name attributed in our VHDL and hopefully assign pins (location) as gathered from XESS manual.

In this instance unable to enter text into Location field...

Rather we must choose Assign Package Pins from User Constraints in Process and enter pins here - then these can be double-checked in the above editor.

7] rerun implement design

Successful!

8] generate bitstream - Generate Programming File

Successful!

9] use xsload to download over parallel port - .bit file (in our project file as defined:

xsload -b xsa-50 -fpga ~/piksel/fpgatests/leddec/leddec.bit

Configure FPGA:
Downloading leddec.bit:fst field: ignoring 9 bytes
100%

(strangely enough produces an error when run from eshell)

in the first example LED decoder from the above URL the xsport utility is used to send bit patterns to the parallel port:

eg:

xsport 101

b) understanding of RAM and I/O pin access with XTEND board - again using example code. also perhaps audio and simple video

I/O pin access (which is used within Implementation Constraints (ucf file)) is simply a matter of looking up pin assignments in the manual. The example above also gives some advice.

Notes on: 20:45 (2006.09.11:4 tech_notes#262 research#69 xxxxx_at_piksel#1 lispcpu#1)

Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode

Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT

To quote from the opening abstract:

We present a design for a class of computers whose 'instruction sets' are based on LISP. LISP, like traditional stored-program machine languages and unlike most high-level languages, conceptually stores programs and data in the same way and explicitly allows programs to be manipulated as data. LISP is therefore a suitable language around which to design a stored-program computer architecture. LISP differs from traditional machine languages in that the program/data storage is conceptually an unordered set of linked record structures of various sizes, rather than an ordered, indexable vector of integers or bit fields of fixed size. The record structures can be organised into trees or graphs. An instruction set can be designed for programs expressed as such trees. A processor can interpret these trees in a recursive fashion, and provide automatic storage management for the record structures.

further - an architecture and an instruction set are specified, fabrication of a VLSI prototype microprocessor is described.

1) LISP as a high-level machine language. Given that "LISP reflects the structure of program expressions in the structure of the data which represents the program." and also given that data and programs are equivalent and can equally be manipulated (within the "incestuous" realm of compilers and interpreters).

2) Tree structure rather than linear vector of instructions which can be indexed using counters and the like. Evaluation by recursive tree-walk.

3) Lisp atoms and lists are described in fine detail with examples prior to the exposition of a meta-circular LISP interpreter (ie. it is written in LISP and can interpret itself).

4) APPLY within this simple interpreter... in the case of primitive procedures:

"... primitive symbols are not to be confused with the atomic symbols used as their names. The actual procedure involved in the combination (car x) is not the atomic symbol CAR, but rather some bizarre object (the value of the atomic symbol CAR) which is meaningful only to PRIMOP-APPLY."

(thus further into the appendix the magic of execution is microcoded)

5) State machine implementation:

An interpreter in the form of a state machine controller. (rendering explicit as a control mechanism that which the recursive LISP interpreter hides - state information that must be saved on each recursive invocation).

Registers and a list memory system.

The evaluator in Lisp has five global registers which simulate the registers of a machine

EXP - hold expression or parts of under evaluation
ENV - holds pointer to environment structure (context)
VAL - value developed in evaluation of expressions
ARGS - list of evaluated arguments
CLINK - pointer to top of the list structure which is the control
stack

Further LISP code such as EVAL-DISPATCH implements the simulation

6) Representing LISP data.

"Lists are normally represented by records each of which contains two pointers to other records. One pointer is the car and the other is the cdr."

(A (B C) D) becomes

 _ _      _ _      _ _
|.|.+ -> |.|.+ -> |.|.+--> NIL
 - -      - -      - -
 |        |        |
 v        |        v
 A        v        D
          _ _      _ _
         |.|.+ -> |.|.+--> NIL
          - -      - -
          |        |
          v        v
          B        C

Pointer representation is unimportant. We give pointer to memory system and it returns the context of the record pointed to. A type field is associated with each pointer.

7) The state machine implementation is combined with typed pointer dispatch to form an interpreter which can be implemented in hardware (p. 15)

8) Storage management:

The system is divided into:

a) a storage system which "provides an operator for he creation of new data objects and also other operators (such as pointer traversal) on those objects."

b) EVAL (program interpreter) which "executes programs expressed as data structures within the storage system"

in classic Von Neumann style.

The storage manager here makes a "finite vector memory appear to the evaluation mechanism to be an infinite linked-record memory". Thus a garbage collector is implemented.

9) Physical layout of the prototype processor

"The evaluator and the storage manager are each implemented in the same way as an individual processor. Each processor has a state-machine controller and a set of registers. On each clock cycle the state-machine outputs control signals for the registers and also makes transitions to a new state."

...

"The contents any register is a pointer (8 bits in the prototype) and a type field (3 bits in the prototype). The registers of a processor are connected by a common bus (E bus in the evaluator, G bus in the storage manager)

....

"Each state-machine controller consists of a read-only memory (implemented as a PLA), two half registers (?) (clocked inverters, one at each input and one at each output), and some random logic (eg. for computing the next state)... two phase non-overlapping clock signals..."

1- registers are clocked. next state is computed

2- next-state signals appear and are latched

all signals from the controllers can be multiplexed onto twelve probe lines

10) Discussion

There is no ALU.

Possible addition of complex processors/devices on the external memory bus with LISP processor serving as controller.

At the same time talks of a layered approach wherein a line can be drawn at arbitrary points within a tower of abstraction = a boundary between evaluator and storage manager

"... a hierarchy of interpreters running in [a] virtual machine. Each layer implements a virtual machine within which the next processor up operates."

such a boundary also exhibits an arbitrary distinction between hardware and software. also the overlap:

"Each of the layers in this architecture has much the same organisation: it is divided into a controller ("state machine") and a data base ("registers"). There is a reason for this. Each layer implements a memory system and so has state; this state is contained in the data base (which may be simply a small set of references into the next memory system down (own note: no operation but only a mapping)). Each layer also accepts commands from the layer above it, and transforms them into commands for the layer below it; this is the task of the controller."

also in talking of analogies between common CPU and CPU here:

"We may loosely say that there are two addressing modes in this architecture, one being immediate data (as in a variable reference), and the other being a recursive evaluation. In the latter case, merely referring to an operands automatically calls for the execution of an entire routine to compute it!"

11) History of VLSI implementation

Typed pointers treated as instructions, with the types as "opcodes" to be dispatched on by a state machine...

Rough sketch of building blocks:

PLA library array cells, simple replicated register cells assembled using (LISP-based) software

12) Conclusion

A CPU "... organised purely around linked records, especially in that the instruction set is embedded in the organisation."

Finally concludes that just as the LISP tree data representation informs this particular instruction set and thus the CPU architecture (for it is not just a question of representation but also changing the means of manipulation), so other representations (for example graphs) or storage organisations could be examined.

13) Appendix - Prototype Lisp Processor Technical Specifications

For later examination.

so far... The Instruction Set:

The 3 byte type field supplies 8 "opcodes":

from 0=constant list to 7=quoted constant

Address part of the word has different purposes dependent on type.

Procedure call (type 6) is the most complicated of all:

"It is a list of indefinite length, chained together by CDR pointers

xx_____

Also of note here is the use of transistors and resistors (in this case depletion-mode transistors) which can be used to construct logic gates.

see also GC probe mux and multiplexor p61,62 - a grid of wires with transistor across for probes

register cell p 63

FPGA research plans:: 17:26 (2006.09.11:3 tech_notes#261 research#68 fpga#1 xxxxx_at_piksel_notes#23)

Notes on: 15:30 (2006.09.11:1 tech_notes#259 xxxxx_at_piksel_notes#22 research#67)

The Design of an M6800 LISP Interpreter, S Tucker Taft, BYTE August 1979

(notes for piksel, instruction sets as steps towards Lisp CPU or any kind of artistic CPU - an examination of hardware-based means of representation. At what point the necessary reduction (or why it is considered as such) into hardware makes sense. Or to keep all levels as a simultaneity. Comparison of high-level with instruction sets. At the same time some way - borrowing from the Lisp CPU - that we can eavesdrop in audio fashion on all internals of the CPU, not just registers a la self.c (own code see software) but also data paths. Indeed if such paths ans such an exposure are implied through a parallel switching architecture. The FPGA is attractive precisely as RECONFIGURABLE architecture or matrix rather than as RECONFIGURED.)

1) Underlying representation of lists using dotted pairs (two address cells). The left cell points to the first element of a list, and the right cell to the rest of the list. NIL is used to signify end of the chain. CONSing two atoms gives a dotted pair with CDR of final dotted pair as non-NIL atom.

(see also diagrams on:

http://www.gigamonkeys.com/book/they-called-it-lisp-for-a-reason-list-processing.html

)

2) READ, EVAL and PRINT loop

Internal representation of the list (the program) is called a form here - the form is evaluated according to the convention that the first element of such a list specifies a function, with the rest of the list as arguments.

3) Into implementation:

BIGLUP LDX PRMPAT  get prompt atom
       JSR PATOM   print the atom
       JSR READ    read the form - result is in x reg
       JSR EVAL    eval the form - result is in x reg
       JSR PRINT
       BRA BIGLUP

PATOM is a subroutine, also used by PRINT when a form is tested as an atom.

M6800 index (X) register - 16 bits long use for all object representations/forms

Dotted pairs must hold two forms - thus 32 bits (4 consecutive memory bytes)

Internal representation for atoms:

For symbolic atoms two items of information are needed:

thus 4 bytes chosen with first 2 as memory address of print name and third of fourth holding value (form) of the atom

A way to distinguish dotted pairs from atoms is needed:

In this instance all dotted pairs and atoms are aligned on 4 byte boundaries which means that we can use the lowest two bits 00 01 to encode type and garbage collection (GC) information.

With numeric atoms name determines value and hence only name (or value) needs to be specified. Representation was chosen with high order bit set, 14 bits numeric value and 1 for GC (seeing as only 0000 through 7FFF is used for atoms and dotted pairs storage bit so when forms specify this high order bit is free.

Special representation for the NIL atom High order byte is zero (which rules out 256 byte page starting at zero).

x_______

A linked list (called OBLIST) of all defined symbolic atoms is used for example by READ and also the EQ function. READ checks prior to allocating 4 byte cell for atome of given print name. If found, returns form specifying the pre-existing atom. Otherwise, copies name into name storage area, allocates 4 byte cell, inits left cell to point to name and right to NIL and returns form.

x_____

READ function

Builds up internal representation - allocating dotted pairs and atoms. If expression is a list READ returns the first dotted pair.

RATOM does the work of allocating new cells as above. Deals with parentheses with recursive calls to READ.

(code p143)

PRINT function

Takes a single form as argument, and types the value as fully parenthesised LISP expression.

EVAL function

The heart of the matter.

EVAL accepts one form as argument and evaluates it according to the convention:

"the value of NIL is NIL, the value of a numeric atom is itself, the value of a symbolic atom is the form associated with the atom, and the value of a list is determined by applying the function specified by the CAR of the list to the list of arguments which make up the CDR of the list."

SUBRs and LAMBDAs: SUBRs as built in functions written in machine code (eg. CAR< CDR< PATOM). LAMBDAs are user defined.

The system here treats the bytes which make up the machine code of the SUBR as the print name of the atom. SUBR specified with dotted pair and car as atom SUBR. Machine code is also prefixed with a special string.

(p147 code listing)

Pask and electrochemical computing: 21:32 (2006.09.05:2 tech_notes#255 xxxxx_at_piksel_notes#21 research#66)

http://homepage.mac.com/cariani/:/PaskPaper.html

http://www.armyofclerks.net/#dendrite

(game of life) in FPGA: 20:39 (2006.08.31:4 tech_notes#254 research#65 xxxxx_at_piksel_notes#20)

http://www.jefspalace.be/digital/game%20of%20life/index.htm

also:

http://www.stanford.edu/class/ee183/tao.shtml (for XESS board and Verilog)

no instruction set but collection of singular parallel instruction/data streams - switching between these (FPGA implementing a reconfiguration itself)

a new architecture

Verilog and VHDL (both HDLs = hardware description languages): 20:20 (2006.08.31:3 tech_notes#253 research#64 xxxxx_at_piksel_notes#19)

Very high speed integrated circuit Hardware Description Language.

description of behaviours (component for example an AND gate) as an entity/architecture pair are combined

links:

http://esd.cs.ucr.edu/labs/tutorial/

http://instruct1.cit.cornell.edu/Courses/ee475/

http://www.arl.wustl.edu/~jst/cse/260/dp/cpu.html

Easier to learn (closer to a programming language), offers variety levels of abstraction

links below:

or even:

Bill Seaman (http://digitalmedia.risd.edu/billseaman/pdf/tb_endoNeo-1.pdf )

Konrad Zuse (ftp://ftp.idsia.ch/pub/juergen/zuserechnenderraum.pdf )

Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf )

Building blocks of an FPGA

logic gates, lookup table, flip-flops (memory)

"The configurable logic blocks (CLBs) in the FPGA can be further decomposed into look-up tables (LUTs) that perform logic operations."

running in parallel. a question of clocks and frequency

further FPGA/CPU links:

http://members.optushome.com.au/jekent/Micro8/Micro8.html

(see Verilog as HDL: http://www.kuro5hin.org/story/2004/2/27/213254/152 )

http://www.frank-buss.de/lispcpu/ 22:34 (2006.08.21:6 tech_notes#245 research#62 waves#2 xxxxx_at_piksel_notes#17)

data paths (registers and operations) and the controller 22:21 (2006.08.21:4 tech_notes#243 research#61 waves#1)

for a CPU:

(again)

http://www.async.ece.utah.edu/~myers/nobackup/ee3700_99/xilinx/lab8.html

from http://www.codesandciphers.org.uk/lectures/ieee.txt 20:50 (2006.08.21:3 tech_notes#242 research#60)

(as looking into encryption/Turing and the vocoder)

So then we built a test rig consisting of a vacuum cleaner motor, some pulleys off a little trolley and that ran tape round and gave signals out from the photocells.

(from riga presentation notes) 13:01 (2006.08.21:2 research#59 xxxxx_at_piksel_notes#16 life_coding#8)

what is life coding - as expressed by the design of a CPU, the design of a simulations machinery after Daniel Galouye (Simulacron 3 - reworked by Rainer Werner Fassbinder as a pure filmic description of Rossler's endophysics, head, eye and camera in electronic transition - zero domain crossing is your reference)?

our model for the CPU, and the question that the idea of the CPU renders is precisely where we draw the line, where we mark a division or passage between hardware and software, a false and delirious division which could be imagined as between the analogue and the digital - the digital and/as a reining in of the analogue - not so much in terms of discretisation but of a forbidden zone far from zero crossing - a forbidden zone which precisely the Schmitt trigger is designed to out-sketch, to eliminate, drawing that wave as squared, as regular noise. A different time-frame for a digitised sine wave which can also stand as a modulation. what carrier?

so there is this drawing of the line which is a question of instructions also, of microcodes which express the most basic operations which can be achieved in terms of raw hardware, of gates opening and closing around a machinery. on the bus. a drawing of the line which is a question of virtual machines - of how that instruction is understood by an underlying machinery. an old tale of abstractions which fits language. the same line-drawing which articulates a progression into high-level code by way of the (termed by computer scientists as incestuous - within a bachelor realm) interpreter (we will meet again under the terms of evaluation) or the compiler.

such allows us to choose as a model for the CPU, the design of a LISP-based processor undertaken by Guy Steele and Gerald Sussman in the 70s at MIT AI labs. the idea here of a layering down to hardware which mimes the same principles or ideas, an equivalence of data and code which marks the incestuous role-play of the interpreter (code into action, into electricity reflexively) and allows for the entry of quotation; quotation implying a system of notation which can equally well be the brackets of the so-called Lisp S-expressions, or ones and zeroes.

http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf

(Lisp typified as high-level machine language)

how we can proceed from the specification of a high-level programming language - conceived a means of active process description and symbolic manipulation - the latter as key to the electric process described here - rather than as, say, a spreadsheet - proceed from this specification to the description in a (software generated) circuit diagram for that which will run or mime this language.

how does quotation take place in hardware?

CPU/instruction sets - Lisp CPU (Steele, Sussman 1979) 20:29 (2006.08.20:2 research#58 xxxxx_at_piksel_notes#15 tech_notes#240)

mimes same design principles across layered vm segments

low level/high level

(Lisp typified as high-level machine language)

further simulations-machinery operates as parallel such micro-/macro-equivalence CPUs

application, environment and interpreter. 15:53 (2006.08.18:1 research#57 tech_notes#237)

In relation to quotation:

We work at the commandline making use of small custom-coded applications. The application is entered and prompts for user input, where necessary, supplying further information and prompts - an interactive application (similar to REPL of a Lisp - a model behaviour). The editor (GNU Emacs) presents an extendible code-face environment whilst at the same time wrapping this with a system of questions and prompts (interrogative). At the same time we can run a Lisp (by way of SLIME also) within Emacs - we can evaluate expressions, define functions, execute code and connect to processes, yet within the prompt model and on the surface of an expression - a necessarily valid expression. In contrast coding our own REPL allows us to enter a new level of prompting where we can define the nature of our own expressions; for example, solely the nesting of brackets. We are within a closed environment.

a filesystem or environment becomes the work 12:05 (2006.08.11:4 research#56 tech_notes#217)

but aside form any consideration of the ACTUAL software

from SICP: 11:01 (2006.08.11:1 research#55 xxxxx_at_piksel_notes#14 tech_notes#214)

In a similar way, we can regard the evaluator as a very special machine that takes as input a description of a machine. Given this input, the evaluator configures itself to emulate the machine described. For example, if we feed our evaluator the definition of factorial, as shown in figure x, the evaluator will be able to compute factorials.

http://mitpress.mit.edu/sicp/full-text/sicp/book/node81.html

also:

In this chapter (five) we will describe processes in terms of the step-by-step operation of a traditional computer. Such a computer, or register machine, sequentially executes instructions that manipulate the contents of a fixed set of storage elements called registers. A typical register-machine instruction applies a primitive operation to the contents of some registers and assigns the result to another register. Our descriptions of processes executed by register machines will look very much like “machine-language” programs for traditional computers. However, instead of focusing on the machine language of any particular computer, we will examine several Lisp procedures and design a specific register machine to execute each procedure. Thus, we will approach our task from the perspective of a hardware architect rather than that of a machine-language computer programmer. In designing register machines, we will develop mechanisms for implementing important programming constructs such as recursion. We will also present a language for describing designs for register machines. In section 5.2 we will implement a Lisp program that uses these descriptions to simulate the machines we design.

instruction sets in relation 21:34 (2006.08.10:6 tech_notes#213 xxxxx_at_piksel_notes#13 research#54)

to open hardware - data sheet exposes instruction set and opcodes (trusted computing in all senses) - or a form of reverse engineering (for reality CPU?) takes place by way of (aural) experiment. from the instruction set we can extrapolate an architecture

by way of SICP:

p492:

"To design a register machine (a traditional computer) we must design its data paths (registers and operations) and the controller that sequences these operations.

data paths as diagram

state machine as controller (?)

5.2 a Lisp program that uses such paired descriptiuons to simulate the machine

see also p384/5 (data as programs):

[fill in]

and p343+ - streams as signals (for further research on piksel/xxxxx overmapping - simulation of RC network and analogue system in relation also to time)

quoted brackets used as representations, as numbers 21:27 (2006.08.10:5 research#53 tech_notes#212)

see Little Lisper p118+ (Friedman et al).

Read, Eval, Print 18:46 (2006.08.10:4 research#52 tech_notes#211)

For our Salo language (which should employ some meta-level of quotes and brackets itself).

what are the possibilities for the SALO code project? 20:41 (2006.08.09:5 tech_notes#205 research#51 life_coding#7)

previously:

An encoding of Salo according to some system or active scheme of representation.

encoding those enframings, insertions and contextual shifts (life as dream as life as dream) enacted by quotation.

a system of notation (software) mapping levels of action, quotation and description (Salo is such a case - in being filmed, in the act of filming a prescribed script - of expanded software). - relation and marking as itself also within Salo - systematics and enacted diagram overlap here is short circuit of the pseudo-scientific rationalism of de Sade and pornographic intent itself. Such a diagram/system of description can be extrapolated in the opposite direction as a system of creation.

also pragmatic notes - source code commentary

prescriptive formulas and recipes

How to produce such a mapping or system of notation - perhaps Lisp-based and making use of indentation and bracketting

and of course 'quotation within the language itself

linear time-line and nesting of action and notation itself

the language of Salo description becomes active language of fm01 creation

so here we have the idea of a paranthesis-led notation. a language which could be interpreted and such interpretation locked to the already noted frames and nested playback

Lisp hardware discussion: 20:49 (2006.08.07:10 research#50 tech_notes#194)

http://www.codecomments.com/archive274-2004-8-253120.html

further on 20:31 (2006.08.07:9 research#49 tech_notes#193)

lisp machine/cpu to clisp bytecode/virtual machine

http://clisp.cons.org/impnotes/intr-set.html

http://clisp.cons.org/impnotes/vm.html

crossing instruction set question with promiscuous (or in the words of Design of LISP-Based Processors... LAMBDA: The Ultimate Opcode, an "incestuous software" realm of software manipulating software as data: "program editors, compilers, interpreters, linking loaders, debugging systems...") coding - such as at core of the viral (extreme promiscuity) - the compiler (... Trusting Trust)).

virtual shared memory model on a VM.

The bytecode can be thought of as being interpreted by a virtual processor. The engine which interprets the bytecode (the implementation of the virtual machine) is actually a C function, but it could as well be a just-in-time compiler which translates a function's bytecode into hardware CPU instructions the first time said function is called.

The virtual machine is a stack machine with two stacks:

STACK - a stack for CLISP objects and frames (Lisp stack). SP - a stack for other data and pointers (Program stack).

Also Pico Lisp looks interesting from VM POV:

http://software-lab.de/ref.html

"First of all, Pico Lisp is a virtual machine architecture, and then a programming language."

"... the one-to-one relationship of language and virtual machine of an interpreted system"

from FAQ:

Would it make sense to build Pico Lisp in hardware?

At least it should be interesting. It would be a machine executing list (tree) structures instead of linear instruction sequences. "Instruction prefetch" would look down the CAR- and CDR-chains, and perhaps need only a single cache for both data and instructions.

Primitive functions like set, val, if and while, which are written in C now, would be implemented in microcode. Plus a few I/O functions for hardware access. EVAL itself would be a microcode subroutine.

Only a single heap and a single stack is needed. They grow towards each other, and cause garbage collection if they get too close. Heap compaction is trivial due to the single cell size.

There is no assembly-language. The lowest level (above the hardware and microcode levels) are s-expressions: The machine language is Lisp.

computer arch. and opcodes 20:16 (2006.08.07:8 research#48 tech_notes#192)

http://www.rdrop.com/~cary/html/computer_architecture.html#simple_cpu

interesting in mention of PIC-based interpreter

(design of modular PIC system for reconfigurable audio)

see also PICBIT:

http://w3.ift.ulaval.ca/~dadub100/files/picbit.pdf

SALO AVI Lisp manipulation 16:44 (2006.08.07:6 research#47 tech_notes#190)

solely referenced by start and end points catalogued as contra to fm01 mantra

yet such points can be entered into the alice.lisp style representation/querying system and film generated which matches certain queries or as a functional response to an investigation

interesting in general and for promiscuOS 16:38 (2006.08.07:5 tech_notes#189 research#46)

Schemix:

Schemix is implemented entirely in kernel space. It implements an arbitrary number of Scheme interpreters, each one separate from the others, and each one attached to some device in the /dev hierarchy.

http://www.abstractnonsense.com/schemix/index.html

Movitz:

The Movitz system aspires to be an implementation of ANSI Common Lisp that targets the ubiquitous x86 PC architecture "on the metal". That is, running without any operating system or other form of software environment. Movitz is a development platform for operating system kernels, embedded, and single-purpose applications. There can potentially be several completely different

operating systems built using Movitz.

More developed: http://common-lisp.net/project/movitz/

check out CVS

At the same time with regard to promiscuOS:: 15:42 (2006.08.07:3 tech_notes#187 research#45)

The two opposing approaches:

1) Low-level modification (patching) of an existent operating system (GNU Linux, Hurd, other candidates?) or creation of x86-based

promiscuOS (virtualised a la Xen or not).

2) High-level sandboxed shared user-space a la ap0202 but as a (user-) space within which software can be compiled or interpreted and executed on a virtual machine layer which implies (an

intentionality of) leakage

...

question 2] below - or more correctly, page fault exception handling 15:32 (2006.08.07:2 tech_notes#186 research#44)

Understanding the Linux Kernel (O'Reilly, Bovet et al.):

p376+

... the Linux Page Fault exception handler must distinguish exceptions caused by programming errors from those caused by a reference to a page that legitimately belongs to the process address space but simply hasn't been allocated yet.

do_page_fault() function (where? - arch/i386/mm/fault.c) is interrupt service routine for the 80x86 arch...

(from Linux Kernel Primer, PTR, Rodriguez et al:)

p238+

hardware interrupt 14 occurs when processor identifies the following conditions/exceptions:

(note exceptions can be classified as faults: the EIP is the address of the instruction that caused the fault - hence allowing instruction to be resumed if the condition is corrected. and if not...)

and from p183+

we find that the page tables are provided by OS to the MMU (Memory Management Unit - note lacking in sat Motorola 68000 and thus uCLinux port) to enable translation between virtual and physical addresses and to allow paging. (thus phys=virtual under uCLinux) - hardware promiscuity is perhaps promoted by this lack of abstraction, this bare equivalence.

3 bit error code is pushed on the stack by control unit when exception occurred:

do_page_fault is charged with handling possible scenarios, first up reads linear address that caused page fault.

mm_struct descriptor is for process memory

bad_area

jump to label bad_area if (what we're interested in) task's memory region does not include the address or address is not in current task's address space

thence:

is it in user_mode -> SIGSEGV

no - then jump to no_context:

if there is not an entry in the exception table for the offending instruction, we end up with oops screen dump

thus:

for promiscuOS, sharing process memory could be achieved at the level of hardware (uCLinux inspired), process memory creation (allocation) or some kind of patch to the page_fault handler (??)

Creating a Process Adress (p392+ O'Reilly)

clone, fork, shared memory space, parent space, COW...

from promiscuOS::

All process memory is (un)intentionally readable and writable by any process or user.

ideas for further exploration: 12:30 (2006.08.07:1 tech_notes#185 research#43)

1] Elementary electronics p123

The bistable multivibrator. Four of these (the last three lacking a fourth transistor (NPN)) are linked on p166 to construct a binary counter which counts input pulses.

2] How does a CPU detect a memory violation?

Simple question. How it knows of memory boundaries and/of running process for SEGFAULT signal (11?) and how could succesfully override?

3] Possible Lisp-coded AVI manipulations of SALO

(of life_coding layers of quotation) for Riga presentation.

as for below 18:27 (2006.08.04:3 xxxxx_at_piksel_notes#11 tech_notes#184 research#42)

see Victor's 4-bit processor:

... the heart of the processor: a microcode instruction sequencer. This circuit turns instruction codewords into control signals that activate other processor components which in turn perform operations.

and this sequencer:

http://www.vttoth.com/vicproc_seq.htm

Perhaps the most interesting question with any processor is this: how do instruction codes (i.e., code words in memory) get turned into electrical signals that in turn trigger various events in the processor, altering its internal state?

as for address decoding this can be done a la ap0201 making use of 74LS573 latch which latches top 8 bits of (15 bit) address and then we can deliver bottom 7 bits straight from the PIC processor. then tell it to read or write to that address (within 32K NVRAM) - program and/or data memory.

CPU organisation notes::

so far we can read and write opcodes/data to/from memory

this is the work of the control unit which opens and closes gates to effect the circuits of execution

(to/from memory:

http://www.cellmatrix.com/entryway/products/applications/smallMemory.html

)

1. Fetch the instruction into an internal instruction register

2. Decode the instruction

3. Select (calculate) the operands (registers) used by the instruction

4. Fetch the operands from memory (CISC only)

5. Execute the instruction

6. Store (write) the result back in the proper place.

1) registers: (immediate storage), accumulator (or define registers such as memory address, memory data, instruction register

D Flip-flop or D Latches

from Wikipedia ( http://en.wikipedia.org/wiki/User:B_rip )::::

The register operations of a digital system are defined by:

• The set of registers in the system

• The microoperations that are performed on the data stored in the registers

• The control that “orchestrates” the sequence of operations in the system

and:

Just as assembly language reflects the architecture of the individual microprocessor, the registers and the elementary operations performed on the data stored in the registers (called microoperations) are described using a “symbolic notation” referred to as a Register Transfer Language (RTL).

A Hardware Description Languages (HDL), like Verilog, also allows us to describe these microoperations. When taken in the context of an HDL behavioral description, these microoperations are collectively known as the Register Transfer Level (RTL). To avoid confusion, for this class, RTL will always be defined as “Register Transfer Language” and alternative terminology (i.e., Dataflow and Behavioral) will be used when describing a Verilog description of a microoperation.

D ← A + B

In this simple example, RTL notation is used to show the contents of registers A and B acted upon by the addition operator with the result placed into register D.

register file and ALU is known as data path.

2) control unit: microcode sequencer (pulses of microcode/data to ALU) - control gates decode the instruction sending signals to ALU or memory - circuits are reconfigured

microprogram - stored sequences in control memory - further abstraction

or hardwired

3) ALU (as below) - combinatorial logic is used - encoded by x bits to effect required arithmetic operation

MUXes and decoders and gates

4) address decoding and memory

5) program counter - binary counter

instruction set is translated into opcodes 17:06 (2006.08.04:2 xxxxx_at_piksel_notes#10 tech_notes#183 research#41)

how implemented on CPU?

fetch instruction (from memory address - question of addressing), decode , fetch result, increment program counter

and on an FPGA?

question also of how address decoding functions

for xxxxx_publication working on some spatialisation of Zuse's 20:33 (2006.08.03:9)

mapped particles in some relation to cellular automata/CPU diagram at all levels of description - simulated particles of CPU-induced hydrogen bomb - impelled design (von Neumann)

day four electronics: 20:29 (2006.08.03:8 research#39 tech_notes#181)

1) tie fence (if it is conductor) to one arm of potentiometer on 40106

circuit constructed

2) chain of floating 74x240s (using all 8). 2 buffer/invretors feed via 0.22 uF (marked 224) into each other and with an LED across the 2nd buffer/invertor and a 1M variable resistor connecting 2 inputs (or only across 2nd as with LED). interesting oscillations... also

pins 1 and 19 tied to gnd to enable the invertors.

range of possible connections.

3) Schmitt trigger from Beam article: positive/negative feedback

negative feedback - 74x240 invertor with resistor across input to output - towards balance point is half Vcc - 240 transmits high frequency waves (see CMOS radio transmitter)

positive - adds to input and steers away from 1/2 Vcc balance zone

240 has single threshold - 14 has two (positive and negative going as per hysteresis)

using negative feedback (resistor from output to input and say 1M input resistor) we can alter hysteresis thresholds

(if it was non-inverting like a 245 we could create + feedback or with 2x 240 in series and with resistor across both)

opcode is selection of a circuit with ref to the ALU 16:19 (2006.08.03:7 research#38 xxxxx_at_piksel_notes#9 tech_notes#180)

for example:

http://www.cellmatrix.com/entryway/products/applications/8bitALU.html

and:

http://www.cs.trinity.edu/About/The_Courses/cs301/04.computer.circuits/04.comp.cir.html

is interesting as it uses Scheme to model the ALU/logic

Konrad Zuse 16:04 (2006.08.03:6 research#37 xxxxx_at_piksel_notes#8 tech_notes#179)

http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/20-relays/zuseadd.html

(but need to find more schematics)

http://web.cecs.pdx.edu/~harry/Relay/Overview.txt

http://hjs.geol.uib.no/zuse/zusez1z3.htm

Calculating Space. Rechnender Raum. Zuse - cellular automata

cellular automata and fpga as possibility. language.

VLSI: 11:32 (2006.08.03:1 research#36 xxxxx_at_piksel_notes#7)

very large-scale integration

http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/toc.html

particularly:

http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch06/ch06.html

Circuit diagrams and bodies relate to each other as the front 08:35 (2006.08.02:1)

and reverse side of the same piece of paper, recto and verso, then "Not even in the worst times of night, with pencil words on your page only Delta-t from the things they stand for?"

from Pynchon and electromysticism. Friedrich Kittler. (Gravity's Rainbow ref. p. 510)

day two of electronics playing 20:23 (2006.08.01:1 research#34 tech_notes#170)

report:

1) avalanche transistor noise:

success with 2n3904s (NPN) as per:

http://willware.net:8080/hw-rng.html

but should do more with either extra 2n3904 as amp:

see: http://willware.net:8080/hw-rng.html

or using 74LS04 (biased by 2.7k resistor across I/O to bias into "linear region" where they act as op-amps

white noise: very quiet

2) modified simple 40106 (Hex inverting Schmitt trigger) acting as

osciillator:

a) standard configuration is

-VR-R--¬
|      |
|  |\  |
-1-| >-|-2-> next stage
|  |/
|
CAP
|
GND

Frequency dependent on R and VR and capacitor (higher uF, lower freq)

b) first step is inserting feedback transistor-based VR between 1 and 2

c) also VR between inputs of successive gates 3 to 1

d) untying capacitors to ground and put LED in transistor circuit

e) connect one of capacitor ends to wire ariel - radio and electromagnetic sensitivity - this will be fence/radio/street performance module:

outline all modules to be made with PCBs

f) used Darlington pair to amplify signal for small speaker

test oggs:

http://plot.bek.no/~crash2005/010806_40106.ogg

http://plot.bek.no/~crash2005/010806_40106_untied.ogg

research ideas:

1) input to 40106 circuit and how we can further effect from outside.

2) place 40106 gates in a loop

3) amplify transitor noise from avalanche

74ls04 21:50 (2006.07.31:4 research#33 tech_notes#169)

This device contains six independent gates each of which. performs the logic INVERT function.

40106 application note 20:22 (2006.07.31:3 research#32 tech_notes#168)

as:

astable or monostable multivibrators

also transistor as variable resistor (obviously voltage controlled) 19:55 (2006.07.31:2 research#31 tech_notes#167)

to add further layer of switching/automation/self-immersion for new synthesiser

also as add-on modules for old neural

circuit page 38 polytronic (DDR electronics kit)

voltage control on base, emitter to ground and resistance flows across positive (of controlled signal) to collector

day one of electronics playing (one week) 17:42 (2006.07.31:1 tech_notes#166 research#30)

program as described previously

1] 555 as astable circuit producing automatic series of pulses 

a la: http://www.doctronics.co.uk/555.htm#astable

- timing portion consisting of 2 resistors and 1 ca[ (4.7 uF)

(one VR light dependent, one 680 ohms determining frequency and high
and low times of each pulse)

2] 555 also as accepting control voltage for frequency - pin 5

3] 555 as monostable trigger

4] Schmitt trigger - 2 transistors as in Polytronic book (2nd
variation with both emitters tied and potentiometer to ground.

addition of a 3rd transistor in place of one potentiometer

new ideas/work/TODO:

1] today maybe tackle RC oscillator (p162 poly) and tone generator
(p104) and compare circuits to basic electronics

2] make simple low-frequency radio circuit for connection to fences,
street furniture (along with regular transmitter) (SEE ABOVE)

3] print all necessary data sheets (DONE)

4] plus all circuit modules outlined.

5] hysteresis in Schmitt triggers as gap between positive and negative
going switching voltage

hysteresis:

a retardation of the effect when the forces acting upon a body are
changed (as if from viscosity or internal friction); esp: a lagging in
the values of resulting magnetization in a magnetic material (as iron)
due to a changing magnetizing force.

see:

http://www.lassp.cornell.edu/sethna/hysteresis/WhatIsHysteresis.html

and also noise in hysteresis in relation to avalanching:

http://www.lassp.cornell.edu/sethna/hysteresis/noise.html

and,

http://www.lassp.cornell.edu/sethna/hysteresis/hysteresis.html


that a schmitt trigger or circuit composed of 19:53 (2006.07.30:4 research#29 xxxxx_at_piksel#2)

can obviously be modelled or simulated in software

this relation of hardware and simulation (running on hardware) for piksel/research as it relates also to (an) interface

see also SICP p273: A Simulator for Digital Circuits

easiest way to deal with bookmarking in w3m/emacs/planner 18:39 (2006.07.30:3 tech_notes#164 emacs#9 research#28)

is M-x remember from w3m buffer (whatever we are browsing) to fill in link automatically as below:

http://1010.co.uk/

but need to research further on Emacs bookmarks, w3m and planner integration - some stuff below already on tech_notes page

[]- 15:03 (2006.07.30:1 xxxxx_at_piksel_notes#5 research#27)

that the interface can solely be a word, any form of signal under the sign of a protocol; no physical connection is implied.

1] to test GRAF 8 bit computer as artefact 11:43 (2006.07.28:1)

[seems to be working though needs a heatsink on the 7805-based PSU - simple tests loading code from EPROM run].

next question is how to input code and save this!

2] electronics - use of 74LS244/245 as current amplifiers

74*04 or 74*240 as plain old invertor

others of interest include 74LS244, 374 buffers

further circuits:

a) relay-driven AND, OR GATES on boards (for piksel artefacts)

b) see also transsitor ODER-Schaltung and UND-Schaltung

c) capacitor and coil as oscillators

x- x-

3] also lisp interpreter for z80 research

brief search refs:

http://www.mcjones.org/dustydecks/archives/2005/06/08/41/

http://community.computerhistory.org/scc/projects/LISP/

http://www.informatimago.com/develop/lisp/lisp15-0.0.tar.gz

further ideas:

code as artefact also

lisp-processor (cells) in FPGA:

more on this on research and particularly xxxxx_at_piksel

Design of LISP-Based Processors or, SCHEME: A Dielectric LISP or, Finite Memories Considered Harmful or, LAMBDA: The Ultimate Opcode

https://www.gelato.unsw.edu.au/archives/comp-arch/2006-May/000903.html

http://del.icio.us/azz/fpga

MyHDL - Python HDL for generation of Verilog: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff

CADR machine: http://home.comcast.net/~prunesquallor/memo528.htm

circuits for synthesiser extension and experimentation: 20:48 (2006.07.26:1)

all to be documented here (particularly PIC 18F programming and PF work)

1) basic transistor circuits (to be completed)

2) RC oscillator

3) simple FM transmit and recieve

4) neural network (74HC14 and 40106) circuits

5) darlington pair

6) op-amps and feedback

7) NOT gate and other logic circuits

8) 555, square wave and further (transistor-based) Schmitt triggers

9) diode/transistor avalanche

10) PIC programming (Broccoli18 see

http://home.earthlink.net/~davesullins/software/pic18f.html )

http://zwizwa.goto10.org/darcs/brood/doc/purrr.txt

11) switch (4016/66) module

12) prototype 74HC595 -> 4016/66 swithces for self-switching circuits

13) using the 4051?

references:

http://library.solarbotics.net/pieces/parts_elect_ic.html

(see the 1381s: these "gate" a source until the voltage is above some "trip" limit, at which point it is allowed onto a third pin. These chips are discriminated by the voltage at which the 1381 triggers, with a single-digit suffix (a.k.a., its "rank") on the part number corresponding to the trip voltage:) there

http://www.retards.org/library/technology/electronics/audio_circuits/synths/diy-synth_list_archive/synth-diy.archive.9510

http://www.cgs.synth.net/modules/cgs28_seq_switch.html

http://www.fairchildsemi.com/pf/CD/CD4051BC.html

http://www.williamson-labs.com/480_xtor.htm

http://boardroom.solarbotics.net/beamod/sonic.html

http://www.solarbotics.net/bftgu/tutorials_schmitt.html

http://www.doctronics.co.uk/4015.htm

http://www.doctronics.co.uk/555.htm

http://www.doctronics.co.uk/4016.htm

http://www.cgs.synth.net/modules/cgs21_super_psycho.html

http://www.uoguelph.ca/~antoon/gadgets/741/741.html

http://www.kpsec.freeuk.com/trancirc.htm

http://www.edn.com/index.asp?layout=article&articleid=CA313057

http://www.geocities.com/vsurducan/electro/PIC/pic84lcd.htm

copied from tech_notes: 15:37 (2006.07.19:3)

1] three basic transistor circuits or configurations.

from our 25 Schaltungen... book:

1) emitter-grundschaltung
2) Kollektor-grundschaltung
3) Basis-grundschaltung

translated as:

TRANSISTOR CONFIGURATIONS

A transistor may be connected in any one of three basic configurations (fig. 2-16): common emitter (CE), common base (CB), and common collector (CC). The term common is used to denote the element that is common to both input and output circuits. Because the common element is often grounded, these configurations are frequently referred to as grounded emitter, grounded base, and grounded collector.

from:

http://www.tpub.com/neets/book7/25f.htm

which further explains these configurations

2] the digital as a hiding or obscuring process in some ways; a falsehood of software further reinforced by a faked exposure: "these ones and zeroes are physical voltages."

3] what is unity voltage gain?

A gain of factor 1 or (equivalent to 0 dB) where both input and output are at the same voltage level is also known as unity gain.

also see:

http://web.telia.com/~u85920178/begin/opamp00.htm

THE SIMPLE EMITTER-FOLLOWER. The simplest discrete circuit-block is the emitter-follower. It acts as a unity-voltage-gain buffer. A buffer is a stage with high input impedance and low output impedance; typically it prevents things downstream from loading things upstream. The simple emitter-follower does not have a gain of exactly one, but it is usually pretty close; this will depend somewhat on the output loading; don't expect the output impedance to be as low as a opamp with plenty of NFB. This page deals only with simple emitter-followers, ie those with one transistor as the actual follower. This count of one does not include extra transistors used as current-sources, etc to improve current-sinking behaviour.

http://www.dself.dsl.pipex.com/ampins/discrete/ef.htm

4] time and the C-R network:

arrival end of essay at the digital.

monostable vibrator

p63 (Penrose - PC interfacing) - monostable with one 555 chip

= 74HC14 quotation from data sheet:

The SN54LS/74LS13 and SN54LS/74LS14 contain logic gates/inverters which accept standard TTL input signals and provide standard TTL output levels. They are capable of transforming slowly changing input signals into sharply defined, jitter-free output signals. Additionally, they have greater noise margin than conventional inverters.

Each circuit contains a Schmitt trigger followed by a Darlington level shifter and a phase splitter driving a TTL totem pole output. The Schmitt trigger uses positive feedback to effectively speed-up slow input transitions, and provide different input threshold voltages for positive and negative-going transitions. This hysteresis between the positive-going and negative-going input thresholds (typically 800 mV) is determined internally by resistor ratios and is essentially insensitive to temperature and supply voltage variations.

stages in the radio from book: 13:09 (2006.07.19:1)

1) the aerial (voltage and wire)
2) the tuner (variable capacitor)
3) the detector (diode)
4) the filter (demodulation)
5) amplification (making audible and visible, voltages are increased.

for waves: 22:20 (2006.07.18:1)

Modulation and demodulation applies equally in the analogue and digital domains; indeed marking an equivalence. An antenna tied equally to software, with reference to the marketing-speak of GNURadio, and to hardware. An equivalence driven by increasing clock speeds, an increasing bandwidth with respect to frequencies which also acts as a driving force in the opposite direction; minimal clock speeds of 8 bit engines rendered visible as obscurantist trends of hardware are exposed by such a disintegrated border with the antenna, the simple detector circuit or one way wire of a detected and always present waveform picked out. The so-called digital is always a question of timing, of clock speeds, of modulation (astable multivibrator, flip-flop). Radio becomes a new reference for software.

We can envisage tiny bit-broadcast circuits at any frequency; preferably as low as the oldest digital circuitry invited into a space dominated by 50 or 60 Hz harmonics. Making that space apparent, through a question to meaning.

for a home-made transistor: 20:40 (2006.07.12:6 research#21 tech_notes#147)

Instead of bothering with tiny wires, Brattain attached a single strip of gold foil over the point of a plastic triangle. With a razor blade, he sliced through the gold right at the tip of the triangle. Voila: two gold contacts just a hair-width apart.

The whole triangle was then held over a crystal of germanium on a spring, so that the contacts lightly touched the surface. The germanium itself sat on a metal plate attached to a voltage source. This contraption was the very first semiconductor amplifier, because when a bit of current came through one of the gold contacts, another even stronger current came out the other contact.

from:

http://www.pbs.org/transistor/science/events/pointctrans.html

software radio using below bt878 16:08 (2006.07.12:5 tech_notes#146 research#20)

http://www.domenech.org/homebrew-sdr/receiver-1.htm

also back to bt878 at 896000 samples per second (442 KHz usable bandwidth) 16:06 (2006.07.12:4 tech_notes#145 research#19)

http://www.domenech.org/bt878a-adc/index-decimator-e.htm

for baudline use and CPU noise analysis 16:01 (2006.07.12:3)

http://www.wisdom.weizmann.ac.il/~tromer/acoustic/

minimal antenna: 14:41 (2006.07.12:2)

http://www.vlf.it/minimal/minimal.htm

started experiments with baudline and stasi radio antenna 13:46 (2006.07.12:1)

50 Hz power lines mirrored at 100 and 150 Hz

(these are harmonics of 50 Hz)

see also:

http://www.techlib.com/electronics/VLFwhistle.htm

and from http://www.vlf.it/kurt/elf.html ::

a number of obviously artificial signals seem to be sended out by some unknown sources permanently, created by electric currents flowing through the surface of the ground and only visible and hearable by using a sound card as a kind of "time microscope".

in context of ripper radio reception

for harmonics see:

http://www.umanitoba.ca/faculties/arts/linguistics/russell/138/sec4/source.htm

and:

http://www.phys.unsw.edu.au/~jw/strings.html#standing

in context of standing waves

For GNURadio we need to get to IF (Intermediate Frequency) 19:18 (2006.07.11:6)

http://en.wikipedia.org/wiki/Intermediate_frequency

An intermediate frequency (IF) is a frequency to which a carrier frequency is shifted as an intermediate step in transmission or reception. It is the beat frequency between the signal and the local oscillator in a radio detection system. IF is also the name of a stage in a superheterodyne receiver. It is where an incoming signal is amplified before final detection is done. There may be several such stages in a superhet radio receiver.

of radio signal

on a Superheterodyne receiver

Heterodyne receivers "beat" or heterodyne a frequency from a local oscillator (within the receiver) with all the incoming signals. The user tunes the radio by adjusting the set's oscillator frequency. In a mixer stage of the receiver, the local oscillator signal multiplies with the incoming signal, producing beat frequencies both above and below the incoming signal. The mixer stage produces outputs at both the sum of the two input frequencies and at the difference. Either the higher or the lower (typically) is chosen as the IF, which is amplified and then demodulated (reduced to just audio frequencies through a speaker).

http://en.wikipedia.org/wiki/Superheterodyne_receiver

for entry into source code of GNURadio:

http://www.gnu.org/software/gnuradio/examples/elenco_fm_demo_no_gui.cc

how do we make an antenna 17:38 (2006.07.11:5)

for experiments with soundcard and analysis software?

from here: http://www.qsl.net/dl4yhf/speclab/vlf_rcvr.htm

For a start, just connect some meters of wire as an antenna to the MIC input of the soundcard and try to listen to a local QRM source (like a TV set). If you can get the system (described below) to work, add a simple LC network parallel to the input as VLF preselector. This will also protect your soundcard if you connect a longer piece of wire. In my own tests I have found that the system is very sensitive even with only passive components (including 2 protection diodes on a 200 meter long wire).

or:

http://www.hard-core-dx.com/nordicdx/antenna/special/vlfactive.html

and http://www.stormloader.com/gkircher/sbhiz/

quote:

This is a simple high impedance converter that plugs into the microphone input of a Soundblaster card. For the circuit to be useful the sound card microphone input must be compatible with electret microphones. Such cards provide not only ground and input terminals but also a supply terminal with a voltage source of a few volts in series with a resistor of a few kiloohms. Most Soundblaster cards use

5V in series with a resistor of 2.2k.

so we need to provide power source.

more for basic waves/electronics research:

http://www.tpub.com/neets/book9/35.htm

and also describing LC network which is described above

[LC circuits behave as electronic resonators, which are a key component in many applications such as oscillators, filters, tuners and frequency mixers. An LC circuit consists of an inductor and a capacitor]

[or try the old stasi antennas]

farmers manual mention of standing waves 15:20 (2006.07.11:4)

http://web.fm/twiki-bin/view/Fmext/

As an aside: 13:04 (2006.07.11:3)

Some versions of Unix have integrated kernel random number sources available through the device file abstractions of /dev/random and /dev/urandom. When present, these devices combine a cryptographically secure random number generator using non-deterministic sources of bits with seed information from many random sources, such as network interrupts, user input, and other external events.

/dev/random generally returns random bytes until it exhausts the available noise in its entropy pool, and then blocks until more entropy has been gathered. It is thus suitable for cryptographic applications and one-time pads, but the time required to generate a given number of random bytes may not be predictable. For security applications, this is generally the best source of random numbers available in the operating system without attaching special hardware.

/dev/urandom returns as many bytes as requested; when it has exhausted the available noise, the bytes it returns are only pseudorandom. It never blocks, and thus has predictable time requirements, but may not be suitable for cryptographic use.

Systems that don't have /dev/random can try the Entropy Gathering Daemon (http://egd.sourceforge.net), a user-space daemon that performs a similar function.

From Will Ware:(from http://www.robseward.com/itp/adv_tech/random_generator/ ) 12:50 (2006.07.11:2 tech_notes#144 research#11)

transistor avalanche mode noise

(also:

http://www.freepatentsonline.com/5728963.html

and from elsewhere:

Just bias it with its base-emitter junction reverse-biased with a resistor in series to limit the current and a supply of about 9V or more. The junction will have avalanche breakdown at about 7V like a zener diode

also in general for transistors see:

http://www.du.edu/~etuttle/electron/elect2.htm

)

and:

http://willware.net:8080/hw-rng.html

(which also mentions /dev/random and entropy sources - see above)

"This circuit uses avalanche noise in a reverse-biased PN junction, the emitter-base junction of the first transistor. The second transistor amplifies it. The first two ALS04 inverters are biased into a linear region where they act like op amps, and they amplify it further. The third inverter amplifies it some more..."

also includes some nice notes/links for PCB fabrication

xxxxx introduction discarded notes: The opening credits 11:59 (2006.07.11:1 research#10 life_coding#6)

Bibliography, index (with reference to J G Ballard's work The Index, which should be read as a condensed, parallel relative of this work), opening credits, within a necessarily non-fictional film perceived - some kind of technologically mediated - and with an equal resort to the staccato frames of an equally digital Turing machine (film as always a digital medium encoded in base 24 most commonly) recording the enigmatic physics of dials and other instrumentation within the V2 rocket (our living - woman as missile). Film thus as the never-fictional in relation to an instruction set which could be documented here in a reverse direction (again a question of reversibility for de Quincey's carriage, for Nietzsche (the eternal return), for Sade, for Klossowski, for computing itself, for Endophysics by way of entropy, for nuclear operations, and for crash/living), a reverse direction to Ballard's The Index (a fiction of an index for a book which does not exist). The instruction set as a never-articulated atrocity exhibition active real, highly fictional - all the components of the re-configurable logic, the hardware, point in that direction. The Atrocity Exhibition itself is an active circuit articulated by the changes in digital circuitry itself which are effected by the instructions. A setting of switches in strict notated time; a transition from 24 fps to 2.7 GHz, TTL or CMOS modulation within an economy, a system of production imapcted by the very wavelength of light.

The so-called (non) fiction of the real lived film constructed with the real effects of a fictional instruction set. A relationship mapped exactly by the (necessarily) viral executable.

Pierre Klossowski's (as Nietzsche) intensities modulations, simulacra and representations re-read within a landscape of active code, of expanded hardware rendering an eternal return:

First one must admit everything that is purely 'automatic': to dismantle an automaton is not to reconstruct a 'subject'. Since perspectivism(ital) is the characteristic illusion of this automaton, to provide it with the knowledge (ital) of this illusory perspective, the 'consciousness' of this 'unconscious', is to create the conditions of a new freedom, a creative freedom.

Pierre Klossowski. Nietzsche and the Vicious Circle (translation by Daniel W. Smith) p39

Alternative opening credits and introduction. An anonymous entity interrogates this introduction. And given that the computer can easily manipulate these symbols it could well prove itself to be such a thing. Capable of writing or saying "I am." These words, the preceding words appear slowly in green text on a rasterising terminal, a low glow; the past thankfully revisited courtesy of the contemporary GNU/Linux commandline. The clatter of a distant teletype provides suitable incidental or ambient soundtrack as the opening credits now roll. A worthy collation of re-framings as practised by the likes of Godard.

The opening credits roll (that first opening quotation from Gravity's Rainbow). Titles. A relation - fiction. naming with real and otherwise assumed names participants in an all real so-called fiction which follows. Karel Reisz' film French Lieutenant's woman acts as a prime example.

A film with a greater reality, a preferred reality than the so-called and psycho-analytically abused terms of the real without a start on the political. with its broa*Gd frame, these credits we speak of and can enter as participants and as a written text, these credits we can very certainly grab hold of. We could speculate as to a future reality Tv show placing celluloid in all surveillance cameras.

From the repetition of the opening quotation it can only be assumed that Friedrich Kittler is also in the cinema, as a Delta-t of time and space expands to embrace a snowy berlin V2 rocket test launch and final destination (predated by a reversible rainbow) in that very cinema - the same Hollywood theatre or more suitably a recorder turn for a kinematographic cylinder in the first black film studio; driven on by the entropy-led demons ushered in by Thomas de Quincey and nursed by Otto Rossler.

Expanded software

Life coding, a practicle or rather poesis-ridden subtitle for xxxxx, is an active interrogation asking a what and a how in relation to both life and code, inscribed by language; electromystic code commentary as a means of practical liberation from the language virus (cutups as early software art) according to Pierre Klossowski. Expanded software, marking a fretful return to proposing a new space, the artistic erased by the same hex-like five crosses (x86) which veil crash as word, as idea - what some would attempt to name again as life but which we will call software. art and thus life in the age of (its impossible, zeroed) mechanical reproduction - better translated as ....

Speculative or expanded software (questionable term itself when we come to embrace hard software) abandons the devilish realm of the hex-infested existent hardware, stepping lightly over the established cultures of scripting and notation, other encodings. As such does it not accord, map over, or in the last instance, ultimately be rendered equivalent to what, in the words of an anonymous question on a live coding panel, is termed life? Without entering into any parallels with theatre or film. The opening credits roll.

cutups - Stewart Home riots.

the actor makes a living, lives through the set piece, the camera movement reveales on a mirror edge by both filmed product (executable) and documentation - the train moving window trick again

source code after the fact.

time reversal

expanded software as that which both is and is not in executable - exactly enacting what it was instructed to do by an overdetermined subject enwrapped within an object oriented knowledge domain - the contained universe of rossler's simulations theory

having it both ways - alice dream mirror of the is, is not

hamlet's gnostic veil of culture and of science

Kloss quote p58 reading backwards

pyncho n electro - deceit also

p412 GR - the system - intro life coding...

that you can make a representation, make a drawing, going further, a film to attempt to get hold of that framing - our own credits here, the scene is described, opening scene and always an awakening (ending of Alice), that framing of/around what could be called "life"

1] life coding starts at the command-line, that horizontal prompt proving a horizon for contemplation

2] reframing of texts here which goes without saying

3] what is expanded software?

consideration of expanded software undertaken within xxxxx, as first step towards life coding

mention .walk of socialfiction.org on same ambulatory terrain S Home mapping walk

expanded software and the impact of the executable on necessarily open hardware. An active examination of electro-mysticism in this regard with reference to Friedrich Kittler's essay Pynchon and Electromysticism:

* .. that elegant blend of philosophy and hardware, abstract change and hinged pivots of real metals which describes motion under the aspect of yaw control...

an equation follows.

(Pynchon Gravity's Rainbow p.239)

* The only difference between military test camp and Schwarzgerat, between Peenemunde and novel, is the technical drawing, which converts itself into poiesis, into the making (das Machen).

grew from two series of events concerned with third space - science blah - speculative hardware/software

crash and xxxxx

3) life coding. sadean life coding and salo as example of expanded

software (hardware also)

Sadean live coding and the deceitful world interface

A bibliography precedes a film which is already held together by a tissue of quotations (written, spoke, gestural simulacra), themselves appearing absurd within a context of degradation, of explicitly cruel acts. Reverse the process, viewing this lengthy textual compendium, reframed texts within the context of an xxxxx thematic, in tandem with a viewing, most probably electronic, of Pasolini's Salo and that bibliography, surrounding documentation also rendered as artefacts. An encoding of Salo according to some system or active scheme of representation.

encoding those enframings, insertions and contextual shifts (life as dream as life as dream) enacted by quotation.

a system of notation (software) mapping levels of action, quotation and description (Salo is such a case - in being filmed, in the act of filming a prescribed script - of expanded software). - relation and marking as itself also within Salo - systematics and enacted diagram overlap here is short circuit of the pseudo-scientific rationalism of de Sade and pornographic intent itself. Such a diagram/system of description can be extrapolated in the opposite direction as a system of creation. We can also calculate strict parallels with the embeddings of simulated worlds/enframings/literary quotation (Zeno)/the circuit diagram within Rainer Werner Fassbinder's Welt am Draht (World on a Wire), and thence to originating text Simulacron Three by Daniel Galouye referenced as an entry into the original domain of Endophysics as described by Otto Rossler (see page xxx).

Sade formulating systems

Sadean life/live coding of an extreme order in obvious relation to Home/Cramer - pornographic coding

decoded by Klossowski, Sade's writing in relation to the executable:

p17

21 recuperation of the possible

p41 execution

120 days - made evident in Salo. the frame. the whore/storytellers relating of an aberration interpreted by a machinery (CPU) of the libertines. rendered executable and electric within that circuitry

a spoken source code within irreversible miasmic air of the chateau

The whores as prime example of Sadean life coders - execution as the final dance, the two hopeful boys embrace at the close of the film cut across the tubular torture garden at the end of the telescope or kaleidoscope (history of) screwing down the iris of the film camera. The apparatus here is also in the circuit, perfect end credits of a stopped down lens sequence. A circuit which could be coaxed to embrace a particular author's death.

p42 What gives Sade's text its disturbing originality is that through him this outside comes to be commented on as something produced within thought

p42 parallel last sentenced to pynchon city plans and the radio (kittler)

also pragmatic notes - source code commentary

prescriptive formulas and recipes

film - a representation of that questionable term "ourselves"

of life ignorant as Sartre's pickup of the process of reproduction

film to be gotten hold of - framed yet in some ways through its own invention reflexive. the pinnacle of the always-fictional snuff movie as a sexual reflexivity in the seedy primal location of Edison's Black Maria or Kinetographic theatre - worth mention of original cylindrical nature of early kinematographic apparatus

film credits - the ability to run time backwards.

film credits - faces/sceens - a symptom or sign before they appear - what will happen contained

can i describe myself? problem already of grabbing hold of something

fatalism -

deceitful world interface with reference to the Magus and Burrough's citation/program in Cities of the Red Night:

instructions/post-description: I recorded a few minutes in all three rooms. I recorded the toilet flushing and the shower running. I recorded the water running in the kitchen sink, the rattle of dishes and the opening and closing and hum of the refrigerator. I recorded on the balcony. Now I lay down on the bed and read some selections from The Magus into the recorder.

I will explain how these recordings are made. I want an hour of Spetsai, an hour of places where my M.P has been and the sounds he has heard. But not in sequence. I don't start at the beginning of the tape and record to the end. I spin the tape back and forth, cutting in at random so The Magus may be cut off in the middle of a word ...")

deceitful interface - in the light also of relation de Sade to (as hinted at by Roessler in xxxxx paper) cartesianism

Because if the world is consistent relationally, then it’s a machine world and then the other human beings that you meet during daily life also are nothing but machines. Then you could in principle build a computer, build an artificial human being, artificial persons. Or at any rate, even if the computer had not been invented yet, where you could build a lower level universe to which you are the boss in the same sense as he felt there was a boss above him. Even before that, with respect to the other people in your world – to you -you can claim that, they are machines. You are outside them in the same way as the vertical exteriority, that imposed the dream of consciousness on you, is outside to you. So this is again a sadistic situation. There was a pupil of Descartes a hundred years later, called the Marquis de Sade who took this element out of Cartesianism, and wrote very cruel books – I didn’t read them – but a friend of mine did and told me the gist: and so one of the sentences is that this young lady : he tells her that it’s her own business, if she loves him. It has nothing to do with him. It’s none of his business to be loved by her. Its just her own pleasure. And this cruelty, it was made possible by Descarte's thinking. If he is the only sensing soul and everybody else is nothing but clay in his hands. So it’s a slavery type situation. So the same slavery type situation that he felt himself to be in, suddenly he is able to give to the next level ( so to speak) suddenly the others become slaves in his own – they are dependent on his fairness or not – and he can mistreat them as machines or he can treat them as machines without mistreating them.

quotation in Salo

temporal bandwidth

a machine for living

a house is a machine for living (dir Pierer Chanal 1931)

enframed machine understood. untied (by capacitor to ground) living less easily represented/understood (recourse to a commonality)

alternating current

waves crossover (see waves text - the circuit)

a machine for living:

living being the task, the role for the machine - that which the machine fulfills. definition of living/life (outside the scientific - again unframed, untied from a domain which could be said to be within living - living from outside endo-living)

living life coding - overlap/frame.

life as dream thematic

sade -> Rossler

crash de quincey trajectory xxxxx

again to cynicism

life as a business, sein und zeit

p195 sloterdijk

by way of Ballard interview, quotation from Villiers de L'Isle Adam's novel ????

As for living, our servants shall do that for us.

echoes in Aldiss - Live? Our computers will do that for us.

again simulation

again live coding/life coding within the frame of a machine for living and of a modern(ist) cynicism

interspersing WaD/simulacra 3 synopsis/lines

preface sloterdijk - public dispute about true living

machine for living (far from utopian sense) - algorithm as enabling a systematics - as a prime mover within an economy of the machine for living - an algorithm of economy. GR as code. cold war explicit as code in being chained in to a kind of hardware - hiroshimic hardware. economy as code. one side of expanded software

4) life as dream thread (how we can enter this). life coding as life/world frame question (endophysics) without entering into

equally brutal term of consciousness

Lightning and Whistler Ghosts 15:34 (2006.07.10:4)

http://www.saao.ac.za/~wgssa/as3/hughes.html

VLF receiver - again just running around for ripper and waves experiments

VLF receiver schematics:

http://www.lwca.org/library/hardware/bbb4rx3.txt

http://www.vlf.it/cr/differential_ant.htm

http://www.geocities.com/CapeCanaveral/Lab/5185/circuit.html:ULTRA

(lots of circuits on the above root)

http://www.radio-flier.com/PDF%20Files/VLF%20Receiver.pdf (not so low 100Hz+)

http://www.infiltec.com/SID-GRB@home/

+ for spectrum analysis

http://www.baudline.com/

Baudline is a time-frequency browser designed for scientific visualization of the spectral domain. Signal analysis is performed by Fourier, correlation, and raster transforms that create colorful spectrograms with vibrant detail. Conduct test and measurement experiments with the built in function generator, or play back audio files with a multitude of effects and filters. The baudline signal analyzer combines fast digital signal processing, versatile high speed displays, and continuous capture tools for hunting down and studying elusive signal characteristics.

question of antenna?

http://www.vlf.it/easyloop/_easyloop.htm (looks possible)

standing waves: ripper (ghost) detector 14:18 (2006.07.10:3)

As an example of the second type, a standing wave in a transmission line is a wave in which the distribution of current, voltage, or field strength is formed by the superposition of two waves propagating in opposite directions. The effect is a series of nodes (zero displacement) and anti-nodes (maximum displacement) at fixed points along the transmission line. Such a standing wave may be formed when a wave is transmitted into one end of a transmission line and is reflected from the other end by an impedance mismatch, i.e., discontinuity, such as an open circuit or a short.

( http://en.wikipedia.org/wiki/Standing_wave )

ripper radio telescope (past): 11:29 (2006.07.10:2)

how much wire wrapped around fence or metal stake in the ground with input into analogue circuitry being across a diode:

x feet of wire (>20) connected to diode= -(!<)- with audio across its contacts

http://my.integritynet.com.au/purdic/radio-telescope.htm

http://hem.passagen.se/communication/uv916rec.html

http://radiojove.gsfc.nasa.gov/telescope/construction_manuals.htm

electromagnetic spectruim obviously includes visible light

microwaves (by way of wikipedia):

Microwaves are electromagnetic waves with wavelengths longer than those of Terahertz (THz) wavelengths, but relatively short for radio waves. Microwaves have wavelengths approximately in the range of 30 cm (frequency = 1 GHz) to 1 mm (300 GHz). However, the boundaries between far infrared light, Terahertz radiation, microwaves, and ultra-high-frequency radio waves are fairly arbitrary and are used variously between different fields of study. The term microwave generally refers to "alternating current signals with frequencies between 300 MHz (3 x 108 Hz) and 300 GHz (3 x 1011 Hz)."1

The existence of electromagnetic waves, of which microwaves are part of the higher frequency spectrum, was predicted by James Clerk Maxwell in 1864 from his famous Maxwell's equations. In 1888, Heinrich Hertz was the first to demonstrate the existence of electromagnetic waves by building an apparatus that produced and detected microwaves in the UHF region. The design necessarily used horse-and-buggy materials, including a horse trough, a wrought iron point spark, Leyden jars, and a length of zinc gutter whose parabolic cross-section worked as a reflection antenna.

for radio/waves research: 11:22 (2006.07.10:1)

// where would software radio enter the story?

Tuners work using a principle called resonance. That is, tuners resonate at, and amplify, one particular frequency and ignore all the other frequencies in the air. It is easy to create a resonator with a capacitor and an inductor (check out How Oscillators Work to see how inductors and capacitors work together to create a tuner).

A system of notation (software) mapping levels of action, quotation 17:05 (2006.07.03:4)

and description (Salo is such a case - in being filmed, in the act of filming a prescribed script - of expanded software). - relation and marking as itself also within Salo - systematics and enacted diagram overlap here is short circuit of the pseudo-scientific rationalism of de Sade and pornographic intent itself. Such a diagram/system of description can be extrapolated in the opposite direction as a system of creation. We can also calculate strict parallels with the embeddings of simulated worlds/enframings/literary quotation (Zeno)/the circuit diagram within Rainer Werner Fassbinder's Welt am Draht (World on a Wire), and thence to originating text Simulacron Three by Daniel Galouye referenced as an entry into the original domain of Endophysics as described by Otto Rossler.

How to produce such a mapping or system of notation - perhaps Lisp-based and making use of indentation and bracketting

and of course 'quotation within the language itself

linear time-line and nesting of action and notation itself

the language of Salo description becomes active language of fm01 creation

the point at which software impacts on hardware 16:25 (2006.07.03:3)

all basic CPU functionalities in a relay-driven hardware

series of recordings entitled as to (logic) components used

diode detector plugs into software

Schottky oscillator (p195 Basic Digital Electronics) - potentiometer in NV net feedback

CPU Instruction Set As an Artistic Object and the History of Classic CPU Instruction Sets 15:26 (2006.07.03:2)

http://www.softpanorama.org/History/cpu_history.shtml

research#2 20:14 (2006.07.02:1)

http://www.graf-automation.de/english/didactic/hardware/computer_basis/

http://zwizwa.goto10.org/darcs/brood/doc/purrr.txt

making use of this software.programmer for the PIC18F:

http://home.earthlink.net/~davesullins/software/pic18f.html

new research areas: 16:01 (2006.06.27:3 tech_notes#141 research#1)

http://www.gnu.org/software/gnuradio/doc/exploring-gnuradio.html#software

also allied to this is obviously high-res/frequency sampling a la

http://www.domenech.org/bt878a-adc/index-e.htm

software radio (from GNU Radio site):

 Software radio is the technique of getting code as close to
the antenna as possible. It turns radio hardware problems into
software problems. The fundamental characteristic of software radio is
that software defines the transmitted waveforms, and software
demodulates the received waveforms. This is in contrast to most radios
in which the processing is done with either analog circuitry or analog
circuitry combined with digital chips. GNU Radio is a free software
toolkit for building software radios.

see xxxxx_at_piksel_notes

[this page - as tech_notes title is maybe too technical]