Additional steps to those outlined:
emerge alsa-firmware
and... modprobe snd_hdsp
Changes also to cur to compile for GCC 4.1.1:
http://1010.co.uk/cur2-rme-feb2007.tar.gz
1] Added library for the older but more manageable FT232BL USB UART (USB to serial) component using online library component builder at:
http://www.rohrbacher.net/kicad/quicklib.php
library is at:
http://1010.co.uk/images/FT232BL.lib
packaging is TQFP32
2] Schematic is at:
http://1010.co.uk/images/atmega8usb.pdf
(note older PCB screenshot is incorrect)
3] 3 projected boards - independent UART and ATmega8 with circles for cpu_model, and both combined as above for 8 bit data interface sans parallel port
rough idea to edit video in Emacs Lisp:
http://www.gnu.org/software/emms/
;; emms-player-mplayer.el --- mplayer support for EMMS (defun emms-player-mplayer-seek (sec) "Depends on mplayer's -slave mode." (process-send-string emms-player-simple-process-name (format "pausing seek %d\n" sec)))
with subtitles and obviously using free software on GNU/Linux...
1] Using mencoder with subtitles specified a la:
/usr/bin/mencoder -of mpeg -mpegopts format=dvd -srate 48000 -ofps 25 -ovc lavc -oac lavc -lavcopts vcodec=mpeg2video:vrc_buf_size=1835:keyint=15:vrc_maxrate=9800:vbitrate=9800:acodec=ac3:aspect=4/3:abitrate=192 thefilm.avi -o test.mpeg2 -sub thesubtitles.srt -font ~/.mplayer/subfont.ttf -subfont-text-scale 3
breaks aspect with dvdauthor: unknown mpeg2 aspect ratio 1
results in DVD image with an incorrect aspect
note also the subfont.ttf as in previous attempts we couldn't scale the font
font can also be specified in ~/.mplayer/mencoder.conf:
font=~/.mplayer/subfont.ttf
Encoding to mpeg2 using ffmpeg works fine with dvdauthor and aspect but using spumux to add subtitles doesn't work - spumux 0.6.13 and darcs version result in drastic memory leaks.
2] Clumsy fix uses two passes:
mencoder thefilm.avi -ovc lavc -oac lavc -lavcopts aspect=4/3 -sub thesubtitles.srt -subfont-text-scale 3 -o outputfilm.avi ## then: ffmpeg -i outputfilm.avi -target pal-dvd -aspect 4:3 test.mpeg2 ## and then the usual processing with dvdauthor /usr/bin/dvdauthor -o ~/dvd -x ~/structure.xml mkisofs -dvd-video -o test.iso ~/dvd/ ##finally growisofs -dvd-compat -Z /dev/dvd=test.iso
for extra good measure dvdauthor's structure.xml:
<dvdauthor>
<vmgm>
<menus>
<video format="pal" aspect="4:3" />
</menus>
</vmgm>
<titleset>
<titles>
<pgc>
<vob file="~/test.mpeg2"/>
</pgc>
</titles>
</titleset>
</dvdauthor>
Computer controlled permutative switching of circuits (allows for 16 points to be connected) using 3 bits (serial data transmission) over USB or parallel port. Modular design of 2 serial/parallel boards (74HC595 shift register chips see: http://computerchristmas.com/index.phtml?link=how_to&:=25) and 4 switch boards (4016/4066 quad bilateral switches): http://www.doctronics.co.uk/4016.htm. Switching points are also exposed to CV (control voltage).
http://users.tkk.fi/~jwagner/electr/dc-rx/PCB_devel.htm
1] Straight print from PCBNEW menu under a range of options is unusable (tracks joined, offset and pads connected randomly).
2] Choose plot with Postscript option from file menu and write (in this case) xxxxx-Component.ps. Printing from this using gv is better but unusable also.
3] Run ps2pdf on this .ps and open resulting .pdf with xpdf. Print from this.
(further notes: print command for our CUPS shared printer is lpr -P printer, resolution was set by way of web interface to 600 dpi)
next stage exposure (UV light) and photoresist:
http://www.electricstuff.co.uk/pcbs.html
dev-lang/python-2.4.3-r1 does not actually support the tk USE flag!
when emerging the gimp:
fix at:
http://www.linuxforums.org/forum/gentoo-linux-help/75725-installing-gnome.html
USE="-tk" emerge -av python
and then emerge gimp (again)
Following: http://thomasgersdorf.com/linux/index.php/Gentoo_Linux_on_IBM_ThinkPad_T60:Fn-Keys
For power management/suspend to RAM and function keys use. No mention of AHCI in Thinkpad BIOS. Enabled sleep states under ACPI in stock 2.6.18 kernel. Emerged: acpid, and thinkpad - previously tpctl stuff also.
xxxxx: rc-update add acpid default
reboot and now: echo -n mem > /sys/power/state
suspends with use of crescent-moon function-F4 to wake up!
Loosely following excellent tutorial at:
http://www.kicadlib.org/Fichiers/:_Tutorial.pdf
as referenced from:
[question remains of how to adapt drawing for mandalas offering up GND, 5V, TX, RD serial circling the central processor - perhaps making use of graphic drawing (only of use on silkscreen layers) and print these at same time]
http://kicad.bokeoa.com/wiki/index.php/Mini_tutorial
http://www.neilvandyke.org/quack/
1] download and (require 'quack) in .emacs
http://www.neilvandyke.org/quack/quack.el
2] default fontlock for ;;; comments (three semicolons) is blue text-invisible bars. change this with:
(setq quack-fontify-threesemi-p nil)
3] Key bindings:
;; The key bindings that Quack adds to `scheme-mode' include: ;; ;; C-c C-q m View a manual in your Web browser. ;; C-c C-q k View the manual documentation for a keyword ;; (currently only works for PLT manuals). ;; C-c C-q s View an SRFI. (Scheme Requests for Implementation) ;; C-c C-q r Run an inferior Scheme process. ;; C-c C-q f Find a file using context of point for default. ;; C-c C-q l Toggle `lambda' syntax of `define'-like form. ;; C-c C-q t Tidy the formatting of the buffer.
Followed instructions at: http://bc.tech.coop/blog/060529.html
(using c key here within Conkeror to copy current link)
and:
http://conkeror.mozdev.org/installation.html
Numbered links: we simply enter the number
To find out more: C-h-i Man page (C- is control M- is meta) or C-h-b - list of all bindings
Simple stuff:
g - open new location
B and F - backwards and forwards
C-x-r-b - jump to bookmark
C-x-r-l - show all bookmarks
ESC to exit text box entry
and usual Emacs bindings - C-s for search which (in caret mode after hitting F7) also highlights and can thus be M-w into killring
One question: how do we access history... history.js?
1] Using old MAX3232 circuit from PIC times (see http://www.geocities.com/vsurducan/electro/PIC/pic84lcd.htm) with pin 11 of 3232 (T1IN) to TX pin 3 on ATmega, 12 (R1OUT) to RX pin 2.
2] 1 MHz is factory default internal oscillator frequency which we CAN change with Guido's prg_fusebit_uc script (1 MHz means we have to stay at 2400 baud and this is as set in minicom: 2400 8N1) - can only be changed without external oscillator upto 8 MHz
3] Sample serial writing code as follows:
#include <stdio.h>
#include <avr/io.h>
#include <inttypes.h>
#define F_CPU 1000000UL // 1 MHz
#include <avr/delay.h>
#define BAUD 2400
#define F_OSC 1000000 //default setting
#define UART_BAUD_RATE 2400
#define UART_BAUD_CALC(UART_BAUD_RATE,F_OSC) ((F_OSC)/((UART_BAUD_RATE)*16l)-1)
void init_uart(void)
{
// set baud rate
UBRRH = (uint8_t)(UART_BAUD_CALC(UART_BAUD_RATE,F_OSC)>>8);
UBRRL = (uint8_t)UART_BAUD_CALC(UART_BAUD_RATE,F_OSC);
// Enable receiver and transmitter; enable RX interrupt
UCSRB = (1<<RXEN) | (1<<TXEN);
//asynchronous 8N1
UCSRC = (1<<URSEL) | (3<<UCSZ0);
}
static int uart_putchar(char c, FILE *stream);
static FILE mystdout = FDEV_SETUP_STREAM(uart_putchar, NULL,_FDEV_SETUP_WRITE);
static int uart_putchar(char c, FILE *stream)
{
if (c == '\n')
uart_putchar('\r', stream);
loop_until_bit_is_set(UCSRA, UDRE);
UDR = c;
return 0;
}
int
main(void)
{
init_uart();
stdout = &mystdout;
while(1) printf("help!");
return 0;
}
4] serial echo (read/write echoes characters typed from miniterm based on wiring.c from Arduino):
http://1010.co.uk/testserial.c
5] Forgot that Emacs/Brood code of Tom Schouten's is all wrapped up in Forth... should be easy enough to use PLT or other Lisp/Scheme to wrap up communications with the scrying scheme board.
6] Next step is to use the LQFP32 packaged FT232BL (not R) board -
Kicad program for schematics looks good but we will have to modify the 232R component (both SMD and DIL ATmegas are available in additional libraries).
links:
Kicad: http://www.lis.inpg.fr/realise_au_lis/kicad/
Libraries: http://www.kicadlib.org/
(Oregano (limited as to component libraries), and Xcircuit also as possible schematic capture offerings).
to edit a schematic and generate a netlist before we make a PCB design in pcb (all GNU free software) - pcb is installed under Gentoo with seperate emerge command.
gschem (also gattrib for editing attributes of .sch files)
http://geda.seul.org/wiki/geda:gschem_ug
and the warmup:
http://www.geda.seul.org/docs/current/tutorials/gsch2pcb/gschem-warmup.html
perhaps try CVS version
Progress so far:
What are the differences here between Default - reference component, embed component and component as individual objects (latter option seperates out and can thus be edited)?
Use reference I think...
ATmega8 component lacks VCC and GND and pin 1 is in an awkward place. First two remedied by modal operation/keystroke driven approach ... where we want pin ap keys and pull line with left mouse into body of chip. middle mouse to stop behaviour. an to add net/wire with similar results. select object with left mouse squaring over and add aa to attach/add attribute such as a pin number. ea to edit attributes of selected piece/element.
er to rotate elements, fs to save, z and Z to zoom, w to zoom next selected square, ve to view extents (?)
But how do we edit the ATmega8 stuff as it stands to switch pin 1?
(only problem is crashes on update)
see Wiki above:
Update Component (ep)
(we can use gattrib to edit attributes which are things like names/values/pin assignments but ...)
warmup above is a good place to start for simple operations.
note also:
it only makes sense to create pins while creating or editing symbol files...
note also url for gattrib: http://www.brorson.com/gEDA/gattrib/
ATmega8 platform, using free software tools, and based on Steele and Sussman's Design of Lisp-based Processors, and Abelson and Sussman's
;;;;EXPLICIT-CONTROL EVALUATOR FROM SECTION 5.4 OF ;;;; STRUCTURE AND INTERPRETATION OF COMPUTER PROGRAMS
;;SECTION 5.4.1 eval-dispatch (test (op self-evaluating?) (reg exp)) (branch (label ev-self-eval)) (test (op variable?) (reg exp)) (branch (label ev-variable)) (test (op quoted?) (reg exp)) (branch (label ev-quoted)) (test (op assignment?) (reg exp)) (branch (label ev-assignment)) (test (op definition?) (reg exp)) (branch (label ev-definition)) (test (op if?) (reg exp)) (branch (label ev-if)) (test (op lambda?) (reg exp)) (branch (label ev-lambda)) (test (op begin?) (reg exp)) (branch (label ev-begin)) (test (op application?) (reg exp)) (branch (label ev-application)) (goto (label unknown-expression-type))
also a pinch of Chaitin's C Lisp interpreter...
http://tuxgraphics.org/common/src2/article352/Makefile.html
in contrast Steele and Sussman make use of a 3 bit type field (plus 8 bits for the address) for 7 types (thus 256x 11 bit words)
#define CONSTANTL 0 #define CONSTANTS 1 #define VAREF 2 #define CC 3 #define PROC 4 #define COND 5 #define PROCEDURE 6 #define QUOTE 7
further storage notes (Steel/Sussman):
The method we use for implementing CAR, CDR and CONS is the usual one of using two consecutive words of memory to hold a list cell, the first being the cdr and the second the car, where each word of memory can hold a type field and an address field. The address part of the pointer is in turn the address within the linear memory of the record pointed to.
Abelson and Sussman use two vectors: the_cars and the_cdrs
http://mitpress.mit.edu/sicp/full-text/book/book-Z-H-33.html
We can use vectors to implement the basic pair structures required for a list-structured memory. Let us imagine that computer memory is divided into two vectors: the-cars and the-cdrs. We will represent list structure as follows: A pointer to a pair is an index into the two vectors. The car of the pair is the entry in the-cars with the designated index, and the cdr of the pair is the entry in the-cdrs with the designated index. We also need a representation for objects other than pairs (such as numbers and symbols) and a way to distinguish one kind of data from another. There are many methods of accomplishing this, but they all reduce to using typed pointers, that is, to extending the notion of “pointer” to include information on data type.7 The data type enables the system to distinguish a pointer to a pair (which consists of the “pair” data type and an index into the memory vectors) from pointers to other kinds of data (which consist of some other data type and whatever is being used to represent data of that type). Two data objects are considered to be the same (eq?) if their pointers are identical.
further:
The reader maintains a table, traditionally called the obarray, of all the symbols it has ever encountered. When the reader encounters a character string and is about to construct a symbol, it checks the obarray to see if it has ever before seen the same character string. If it has not, it uses the characters to construct a new symbol (a typed pointer to a new character sequence) and enters this pointer in the obarray. If the reader has seen the string before, it returns the symbol pointer stored in the obarray. This process of replacing character strings by unique pointers is called interning symbols.
cons as:
(perform (op vector-set!) (reg the-cars) (reg free) (reg <reg2>)) (perform (op vector-set!) (reg the-cdrs) (reg free) (reg <reg3>)) (assign <reg1> (reg free)) (assign free (op +) (reg free) (const 1))
further instruction summary:
A controller instruction in our register-machine language has one of the following forms, where each <inputi> is either (reg <register-name>) or (const <constant-value>). These instructions were introduced in section 5.1.1: (assign <register-name> (reg <register-name>)) (assign <register-name> (const <constant-value>)) (assign <register-name> (op <operation-name>) <input1> ... <inputn>) (perform (op <operation-name>) <input1> ... <inputn>) (test (op <operation-name>) <input1> ... <inputn>) (branch (label <label-name>)) (goto (label <label-name>)) The use of registers to hold labels was introduced in section 5.1.3: (assign <register-name> (label <label-name>)) (goto (reg <register-name>)) Instructions to use the stack were introduced in section 5.1.4: (save <register-name>)
http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-453.pdf
further Scheme research:
icbins: from http://www.accesscom.com/~darius/
with further interesting code there...
from the README from icbins:
Here we have an exercise in stripping a Lisp to barest essentials, dropping the host tether early, and repeatedly changing and rebuilding, to practice evolving a self-hosted system. Only the garbage collector and the lowest-level Lisp primitives are in C. The source is an order of magnitude smaller than the already-lightweight UTS's. You might find this of interest if you want to do similar exercises or if you'd just like to read a tiny Lisp system with no magic (small self-hosting Lisps typically rely on powerful primitives like READ, PRINT, and GC). This could be cut down further; hopefully I'll come back to it someday.
-a) checl we have ftdi_sio and usbserial modules built and loaded
a) we have the Arduino codebase
b) on Gentoo: emerge crossdev (had to first set PORTDIR_OVERLAY=/usr/portage in /etc/make.conf)
takes some time...
c) emerge avrdude programming utility AFTER b) succeeds
d) check out Makefile and modify as below
# Arduino makefile # # This makefile allows you to build sketches from the command line # without the Arduino environment (or Java). # # The Arduino environment does preliminary processing on a sketch before # compiling it. If you're using this makefile instead, you'll need to do # a few things differently: # # - Give your program's file a .cpp extension (e.g. foo.cpp). # # - Put this line at top of your code: #include <WProgram.h> # # - Write prototypes for all your functions (or define them before you # call them). A prototype declares the types of parameters a # function will take and what type of value it will return. This # means that you can have a call to a function before the definition # of the function. A function prototype looks like the first line of # the function, with a semi-colon at the end. For example: # int digitalRead(int pin); # # Instructions for using the makefile: # # 1. Copy this file into the folder with your sketch. # # 2. Below, modify the line containing "TARGET" to refer to the name of # of your program's file without an extension (e.g. TARGET = foo). # # 3. Modify the line containg "ARDUINO" to point the directory that # contains the Arduino core (for normal Arduino installations, this # is the lib/targets/arduino sub-directory). # # 4. Modify the line containing "PORT" to refer to the filename # representing the USB or serial connection to your Arduino board # (e.g. PORT = /dev/tty.USB0). If the exact name of this file # changes, you can use * as a wildcard (e.g. PORT = /dev/tty.USB*). # # 5. At the command line, change to the directory containing your # program's file and the makefile. # # 6. Type "make" and press enter to compile/verify your program. # # 7. Type "make upload", reset your Arduino board, and press enter to # upload your program to the Arduino board. # # $Id$
in:
http://1010.co.uk/arduino/Makefile
e) test code:
http://1010.co.uk/arduino/blink1.cpp
make: avr-g++: Command not found
next try: (after: http://www.arduino.cc/playground/Linux/Gentoo )
USE='-nocxx' emerge cross-avr/gcc cross-avr/avr-libc
make succeeds - we have a blink1.hex and so on
f) make upload
...
few changes to Makefile for avrdude and avrusb500 programmer, updated to new core Arduino necessitating more Makefile changes and now programs fine with 5v attached to ATmega on breadboard
g) pin mapping: http://www.arduino.cc/en/Hacking/
eg. digital pin 13 in blink LED example is true ATmega8 pin 19
// On the Arduino board, digital pins are also used // for the analog output (software PWM). Analog input // pins are a separate set. // ATMEL ATMEGA8 / ARDUINO // // +-\/-+ // PC6 1| |28 PC5 (AI 5) // (D 0) PD0 2| |27 PC4 (AI 4) // (D 1) PD1 3| |26 PC3 (AI 3) // (D 2) PD2 4| |25 PC2 (AI 2) // (D 3) PD3 5| |24 PC1 (AI 1) // (D 4) PD4 6| |23 PC0 (AI 0) // VCC 7| |22 GND // GND 8| |21 AREF // PB6 9| |20 AVCC // PB7 10| |19 PB5 (D 13) // (D 5) PD5 11| |18 PB4 (D 12) // (D 6) PD6 12| |17 PB3 (D 11) PWM // (D 7) PD7 13| |16 PB2 (D 10) PWM // (D 8) PB0 14| |15 PB1 (D 9) PWM // +----+
h) one problem with Scheme/Arduino plan is presented by wiring.c which wraps setup and loop into main function.. but we could easily replace this
in x86 assembly
http://www.stripedgazelle.org/joey/dream.html
note:
The design for the 'dream' Scheme interpreter began with the design given in Abelson and Sussman's Structure and Interpretation of Computer Programs.
also:
again, chapter five of SICP:
from: http://www.ida.liu.se/~tobnu/scheme2llvm/
This is a small (about 1K lines) self applicable scheme toy compiler which compiles to C-code, and a version that compiles to LLVM with the types fixnum, symbols, strings, functions and vectors (cons cells are seen as vectors of size 2).
and:
The code is quite similar to the code in SICP (Structure and Interpretation of Computer Programs), chapter five, with the difference that it implements the extra functionality that SICP assumes that the explicit control evaluator (virtual machine) already have. Much functionality of the compiler is implemented in a subset of scheme, c-defines (llvm-defines), which are compiled to C-functions (llvm functions).
code for SICP at:
http://mitpress.mit.edu/sicp/code/index.html
[also within alice/kodiak.lisp representation import/export of worlds]
also as performative expansion of xxxxx_at_interface
on the one hand, now that which we can call alice, the environment based on the existent (GNU Emacs and beyond)
on the other hand the existent cpu or hardware (either as fpga or using the ATMega (see cpu link)
environment and series of (preferably networked, interpretative, bit spouting) CPUs within the black marias cpu_model connected by way of serial (and thus USB, or Ethernet using the ENC28J60 from Microchip)
also interface to paper circuits.
Film before Film: What Really Happened Between the Images? (1986) by Werner Nekes
(position of Edison and Black Maria studio within such a history)
Universal Dovetailer. Generation of FPGA HDL. Language generation.
Code stepper.
import/export of both evaluatable code and code environments. OSC.
continuations. leakage. representation (our language finally).
Chapter 5: Computing with Register Machines
walking through a Scheme interpreter and compiler for hypothetical (simulated in this instance) stack-based register machine (minus (as simulated in Scheme) various primitive operations such as car, cons))
for such primitives (and a similar implementation) also see:
http://www.frank-buss.de/lispcpu/lispcpu.lisp.txt
(defconstant primitives '#(+ - < > <= >= /= = * set quote setq defun progn get-time set-time set-led get-led while cons car cdr if))
Storage of car, cdr structures is outlined in section 5.3 p533. also garbage collection
towards lispcpu, also perhaps ATMega interpreter/compiler
Lets you place hyperlinks and shell/tcl/TeX/etc code inside plain text files.
from:
http://www.mat.puc-rio.br/~edrx/emacs.html
note also:
Emacs and eev, or: How to Automate Almost Everything
http://angg.twu.net/eev-article.html
with possible use for promiscuOS see:
http://angg.twu.net/eev-article.html#.channels
The way that we saw to send commands to a shell is in two steps: first we use M-x eev in Emacs to send a block of commands, and then we run `ee' at the shell to make it receive these commands. But there is also a way to create shells that listen not only to the keyboard for their input, but also to certain communication channels; by making Emacs send commands through these communication channels we can skip the step of going to the shell and typing `ee' --- the commands are received immediately.
(making use of netcat - netcat as key possible tool for promiscuOS)
OpenGL renderer string: ATI MOBILITY FireGL V5200 Pentium 4 (SSE2) (FireGL) (GNU_ICD)
but also needed to rmmod and then modprobe:
ipw3945 for wireless
vague notes: xterm -ls option to read .bash_rc, win32codecs in USE flags for streaming firefox/mms/wmv:
with thanks to:
http://zerlinna.blogweb.de/archives/73-Watching-Video-streams-mms-and-rtsp-protocol.html
unrelated: at 23c3: http://www.lochraster.org/etherrape/
ethernet for the atmega...
Gentoo install functioning. Notes:
wired untested. wireless working
echo "x11-drivers/ati-drivers ~x86" >> /etc/portage/package.keywords
using fglrx in xorg.conf but no hardware OpenGL as first complained of lack of fglrx_dri.so in /usr/lib/dri - made this directory and copied across but no luck (undefined symobols there) - to be fixed
unrelated: to check out clfswm Lisp window manager
we need fltk as use flag in /etc/make.conf
# These settings were set by the catalyst build script that automatically built this stage
# Please consult /etc/make.conf.example for a more detailed example
CFLAGS="-march=prescott -O3 -mtune=i686 -msse3 -fomit-frame-pointer -pipe"
CHOST="i386-pc-linux-gnu"
CXXFLAGS="${CFLAGS}"
VIDEO_CARDS="fglrx vesa fbdev"
INPUT_DEVICES="keyboard mouse synaptics"
FEATURES="sandbox ccache distlocks autoaddcvs parallel-fetch"
MAKEOPTS="-j3"
GENTOO_MIRRORS="ftp://ftp.tu-clausthal.de/pub/linux/gentoo http://distfiles.gentoo.org http://www.ibiblio.org/pub/Linux/distributions/gentoo"
USE="ibm dvd alsa cdr fltk"
SYNC="rsync://rsync.gentoo.org/gentoo-portage"
links:
and:
http://bellet.info/laptop/t60p.html
Gentoo as preferable:
http://buzzy.tesuji.org/thinkpad_t60p.html
and:
http://www.thinkwiki.org/wiki/Installation_instructions_for_the_ThinkPad_T60p:Kernel_Settings
potential installation from Ubuntu LiveCD 6.10 which recognises Ethernet and Wireless so far:
http://www.gentoo.org/doc/en/altinstall.xml (Knoppix here).
Using the AVR programmer USB, stk500 V2 compatible from:
http://shop.tuxgraphics.org/electronic/microcontroller.html?id=2b93dd
(with thanks to Guido)
Further documentation online at:
http://www.tuxgraphics.org/electronics/200510/article05101.shtml
and also for avr-gcc:
http://www.tuxgraphics.org/electronics/200411/article352.shtml
notes:
mkdir /tmp/mnt
mount -o loop /mnt/cdrom/KNOPPIX/tgr/avr.img /tmp/mnt
cd /tmp/mnt
find avr* | cpio -dump /usr/local/
cd ; umount /tmp/mnt
# and add bin to PATH.
PATH=${PATH}:/usr/local/avr/bin/
export PATH
Makefile is at:
http://main.linuxfocus.org/common/src2/article352/Makefile.html
and uses avr-gcc, avr-objcopy and prg_load_uc shell script which references:
avrdude -p m8 -c avrusb500 -e -U flash:w:"$pfile"
prg_fusebit_uc is also used to "read and write fuse bits of the atmega8"
AvrUsb500 Programmer Kit
mentioned below (notes on this to follow).
http://www.arduino.cc/playground/uploads/Learning/Makefile
# This makefile allows you to build sketches from the command line # without the Arduino environment (or Java). # # The Arduino environment does preliminary processing on a sketch before # compiling it. If you're using this makefile instead, you'll need to do # a few things differently: #
then compiles and links with Arduino library .c (and .cpp) files
and further compiles using avr-gcc, avr-objcopy and so on and uploads with avrdude.
or rather:
an interpreter or vm (virtual machine) in flash
http://amforth.sourceforge.net/
as in:
amforth is a distribution of Forth running on the AVR ATmega microcontroller. Once put into flash, it needs only a serial connection to the host computer. New words are compiled directly into flash, thus extending the dictionary immediately. It is ans94 Forth oriented with some minor exclusions and a few words from the extension word sets. It is written in assembly language and Forth itself. The main development uses ATmega8 and ATmega32 controllers; other ATmega controllers should work with small adjustments.
http://1010.co.uk/audioprinter.c
gcc audioprinter.c -o audioprinter cat /dev/mem | ./audioprinter
Following Pascal Bourguignon's advice (http://www.informatimago.com/linux/emacs-on-user-mode-linux.html).
A few points:
(global-set-key "^\" 'keyboard-quit) ;; strangely, C-g does not work.
from /emacs/.emacs
emacs: Terminal type linux is not defined.
mkdir -p /emacs/usr/share/terminfo cp -R /usr/share/terminfo/* /emacs/usr/share/terminfo/
1] No go with slackware 7.1 rootfs downloaded.
2] re-attempt Emacs on UML with present 21.4 source. In final linking now we have a segmentation fault:
Dumping under names emacs and emacs-21.4.1 make[1]: *** [emacs] Segmentation fault make[1]: *** Deleting file `emacs'
same as for 21.3 source... and with or without static flags ...
3] now thanks to:
http://article.gmane.org/gmane.emacs.devel/17457
[Re: Unable to bootstrap GNU Emacs 21.3 (SOLVED)]
and no thanks to:
"[...] Exec-shield is a security-enhancing modification to the Linux kernel that makes large parts of specially-marked programs _ including their stack _ not executable. This can reduce the potential damage of some security holes. Exec-shield is related to the older "non-exec stack patch" but has the potential to provide greater protection.
Exec-shield can also randomize the virtual memory addresses at which certain binaries are loaded. This randomized VM mapping makes it more difficult for a malicious application to improperly access code or data based on knowledge of the code or data's virtual address.
[...]
Exec-shield functionality is available only to binaries that have been built (and marked) using the toolchain (compiler, assembler, linker) available with Fedora [...]"
turn it off:
1] kernel level (which could also include some kind of dissolution at the network level).
2] application or user level -
and the 1] 2] boundary as leakage = UML (User Mode Linux) - kernel as userland app
quick UML notes:
1] grabbed a 2.6.19 kernel from: http://ftp.ca.kernel.org/linux/kernel/v2.6/
bunzip2 linux-2.6.19.tar.bz2 tar xvf linux-2.6.19.tar cd linux-2.6.19 make defconfig ARCH=um ## default configuration make ARCH=um
2] Results in... linux. Then run ./linux
3] No filesystem!
So, relying on [[http://www.informatimago.com/linux/emacs-on-user-mode-linux.html][Emacs on UML]] we can make a filesystem as follows:
cd ~/uml dd if=/dev/zero of=root_fs_emacs bs=1k count=200k yes y|mke2fs root_fs_emacs # note that yes command outputs string y repeatedly mkdir /emacs mount -o loop root_fs_emacs /emacs cd /emacs ln -s . emacs # we create this link to simplify config --prefix of emacs cp -a /dev dev # we boldly copy the whole /dev mkdir etc sbin tmp # some other directories not installed by emacs cat >etc/fstab <<EOF /dev/ubd0 / ext2 defaults 0 1 EOF
4] Following steps to statically link Emacs-22 fails:
: warning: Using 'getservbyname' in statically linked applications requires at runtime the shared libraries from the glibc version used for linking /usr/lib/gcc/i386-redhat-linux/3.4.2/../../../libc.a(mktime.o)(.rodata+0x0): multiple definition of `__mon_yday' mktime.o(.rodata+0x0): first defined here /usr/lib/gcc/i386-redhat-linux/3.4.2/../../../libc.a(mktime.o)(.text+0x0): In function `__mktime_internal': : multiple definition of `__mktime_internal' mktime.o(.text+0x373): first defined here /usr/bin/ld: Warning: size of symbol `__mktime_internal' changed from 1502 in mktime.o to 2546 in /usr/lib/gcc/i386-redhat-linux/3.4.2/../../../libc.a(mktime.o) collect2: ld returned 1 exit status make[1]: *** [temacs] Error 1 make[1]: Leaving directory `/root/emacs-22.0.91/src' make: *** [src] Error 2
5] Filesystems from uml/sourceforge eg.tomsrtbt fail at INIT or elsewhere - construct from scratch.
1] sans TCP:
see: httpd.el -- a web server in Emacs Lisp
at: http://www.chez.com/emarsden/downloads/
notes:
:: Since Emacs does not (yet!) provide server sockets, you ;; need a helper program to bind to the socket and forward requests. ;; There are two ways of doing this: use a service like inetd to ;; launch a fresh emacs instance for each incoming request, or use a ;; program which forwards requests via gnuserv. The second method ;; obviously provides better performance.
eg:
;; 8080 stream tcp nowait.10000 nobody /usr/bin/emacs emacs -batch \ ;; -l /path/to/httpd.el -f httpd-serve
or use httpd-serve Python script... (from where?)
or see:
muse-http.el file that can turn Emacs into a webserver, much like the emacs-wiki-httpd.el module, except that it doesn't need an external Python script.
muse-http handles requests by way of httpd.el later version:
http://sacha.free.net.ph/notebook/emacs/muse/httpd.el
with lines:
(defun httpd-start (&optional port) (interactive (list (read-input "Serve Web requests on port: " "8080"))) (if (null port) (setq port 8080) (if (stringp port) (setq port (string-to-int port)))) (if httpd-process (delete-process httpd-process)) (setq httpd-process (open-network-stream-server "httpd" (generate-new-buffer "httpd") port nil 'httpd-serve)) (if (eq (process-status httpd-process) 'listen) (message "httpd.el is listening on port %d" port)))see also:
http://www.emacswiki.org/cgi-bin/wiki/rcirc.el
2] In GNU Emacs reference manual:
Emacs Lisp programs can open TCP network connections to other processes on the same machine or other machines. A network connection is handled by Lisp much like a subprocess, and is represented by a process object. However, the process you are communicating with is not a child of the Emacs process, so you can't kill it or send it signals. All you can do is send and receive data. delete-process closes the connection, but does not kill the process at the other end; that process must decide what to do about closure of the connection.
3] Gnuclient and gnuserv:
Gnuserv: It allows arbitrary Emacs Lisp commands to be sent to an Emacs process running either on the local machine or on another machine on the network.
http://linuxgazette.net/issue29/marsden.html
4] ebby - shared Emacs buffers for collaborative editing (no link)
(on this thread:
http://technomancy.us/blog/post/45 and:
http://bc.tech.coop/blog/060509.html)
and thus:
5] Distel: http://bc.tech.coop/blog/060111.html
TODO::
what is already in planner/emacs-wiki to make such grouping possible?
(add-to-list 'remember-planner-append-hook 'planner-rss-add-note t)
called in: remember-planner-append (&optional page) within remember/remember-planner.el
deosn't work. we need to know what exactly is a note.
see ~/elisp/snuff.el:
(emacs-wiki-published-name (planner-note-page info))
need to know how pages are organised
simple version control
rcsintro - introduction to RCS commands
DESCRIPTION
The Revision Control System (RCS) manages multiple revisions of files. RCS automates the storing, retrieval, logging, identification, and merging of revisions. RCS is useful for text that is revised frequently, for example programs, documentation, graphics, papers, and form letters.
The basic user interface is extremely simple. The novice only needs to learn two commands: ci(1) and co(1). ci, short for `check in', deposits the contents of a file into an archival file called an RCS file. An RCS file contains all revisions of a particular file. co, short for `check out', retrieves revisions from an RCS file.
RCS as created directory under project sub-directory
rcsmerge is used in our xxxxx_publication version control text:
rcsmerge -p -A -r1.1 -r1.6 alice > version_control
how this could be integrated with emacs-wiki/planner for automatic generation of merge files
SBUML is an extension to User-mode Linux(UML) that can save complete Linux runtime states in mid-execution(including all hard disks, devices, processes, and kernel space). The same state can be restored at a later time on the same PC, or migrated to another PC. The states can be delta compressed to a few megabytes or less, making it practical to download running Linux machines from websites.
functionality to Emacs/Emacs-wiki:
1] Helpful here is C-x h k (in this case, otherwise C-h k) to see what function keystroke calls, or use M-x apropos and in either case browse to underlined function and hit return to jump to code.
2] If we then need to view code for another function at point then we can use C-x h f (in this case: in other C-h f).
3] Looking at how to read from minibuffer and use in interactive mode in Emacs Lisp:
http://xahlee.org/elisp/Using-Interactive.html
4] Final code:
(defun cat-add (&optional string) (interactive (let ((string (read-from-minibuffer "mytag:"))) (list string))) (insert "<category domain=\"http://1010.co.uk\">" string "</category>"))result - but we just want to pass to rss feed:
<category domain="http://1010.co.uk">emacs</category>
but in rss it should come just before
</item>tag
problem is rss is parsed/created at last moment of publishing - we could search and get it to insert this in the right place
by way of http://bc.tech.coop/blog/061119.html
mosref running with mosquito-lisp
TODO for data_radio project and also promiscuOS
also to note:
http://en.wikipedia.org/wiki/WASTE
and (for promiscuOS): http://www.vanheusden.com/listenpipe/
Listenpipe can be used to sit between 2 applications that are interfaced with pipes. It will pass through data as is but also store what is send/received in a logfile as well.
for leaking pipe code
by way of:
http://bc.tech.coop/blog/061115.html
MzScheme on OSKit: http://download.plt-scheme.org/mzscheme/mz-103p1-bin-i386-kernel-tgz.html
Emacs standing alone on a Linux Kernel: http://www.informatimago.com/linux/emacs-on-user-mode-linux.html
some possible uses for promiscuOS
first prototype:
1] GNUS related: http://www.zarb.org/~gc/html/howto-adopt-gnus.html
2] For planned noise/re-purpose workshop in Berlin:
Mix 555 with finger timing addition, 40106 and transistors on etched board with possile connections - or a series of modules, the transistor NAND gate also.
[paper radio receiver - question of the diode]
3] Also possibly for workshop - paper noise circuit/computer with capacitance between traced sheets:
Wide frequency range oscillators with homemade variable capacitor:
http://home.earthlink.net/~lenyr/varelec.htm
4] Planned workshops: Python, PD, electronics, PIC, VLF, TV transmission, FPGA, Pure:dyne, goto10
with advice from:
http://lifelogs.com/spam/spam.html
and:
http://paste.lisp.org/display/4589
(setq spam-use-BBDB nil
spam-use-stat t
spam-split-group "mail.spam"
spam-stat-split-fancy-spam-group "mail.spam"
spam-install-hooks t)
(setq nnmail-split-fancy
`(| (: spam-split)
;; insert usual split rules in split-fancy syntax
"mail.misc"))
(from http://sacha.free.net.ph/notebook/emacs/planner-config.el )
Evaluated http://elisp.info/package/rss-helper/rss-helper.el
and used rss-helper-gnus-subscribe
which subscribes gnus to rss feed by way of url...
but gives no such newsgroup error after specify the title.
By way of:
http://www.emacswiki.org/cgi-bin/wiki/
technique as follows works:
from Group buffer: G m and group name (eg. 1010test) with nnrss as backend, then when we ENTER for the first time, we are prompted for a URL to search for the feed...
the result looks like:
. [ ?: nobody ] http://www.voti.nl/blink/index_1.html 17:28 . [ ?: nobody ] 16:02 . [ ?: nobody ] link to interface and society slides: 12:54 . [ ?: nobody ] interface and society presentation: 03:00 R. [ ?: nobody ] 03:11
as PIC test reference
1] Kasparov chess interface:
8x8 touch switch interface potentially for FPGA.
we have 8+8 wires from switches - these are pulled high (6v) to low (0.5v) when switched
2] 4016/4066 digital switch tests:
On breadboard, we can switch an (audio) signal (I/O (Y0, Z0) on pins 1 and 2, enable E0 on 13, 6v on 14 and GND on 7). E0 is tied with a 10K pull down resistor to GND so that bringing E0 high will allow Y0, Z0 current.
3] Transistor regulating voltage:
2N3904. CBE viewed upright from back (non-flat).
CV is by way of 10K resistor to base, emitter to output and by way of 4.7K incoming signal.
4] Further brood/cat/purrr meanderings:
a) Latest darcs pull doesn't seem to work, complains of unbound variable for -e purrr and some other problem for emacs cat.el which in principle seems to work well with older version. M-x cat after eval-buffer.
b) Following new steps with previous brood pull (pre-piksel):
(18f sheepsint) restore (after downloading: http://goto10.org/~tom/18f/sheepsint-20060914.tar.gz )
then connect-default...:
error: (not-found connect-default)
still no ping...
c) Troubleshooting serial connection. Incoming serial (black RX on pin 10) seems fine. Outgoing from pin 9 of PIC18F1220 not. Tested with different PICs, MAX3232 still nothing. Sometimed random characters (numbers) from a ping.
In theory:
1] export XILINX=~/Xilinx // where we have our Xilinx distribution
2] ~/Xilinx/bin/lin/promgen -u 0 ~/piksel/fpga_src/tutorail2/tutorial.bit -p exo -s 2048 // make EXO file from our VGA project bitfile
3] xsload -b xsa-50 -flash ~/piksel/fpga_src/tutorail2/tutorial.exo // downloads to the board
to test the last step:...
TESTED on T20 (though strangely xstest fails)
[ see further: http://www.xess.com/manuals/xstools-v4_0.pdf ]
(setq planner-rss-base-url "http://1010.co.uk/")
test3
is a sophisticated electrical CAD system that can handle many forms of circuit design, including:
http://www.gnu.org/software/electric/
http://www.staticfreesoft.com/jmanual/
other schematic-oriented free softwares:
gschem: http://www.geda.seul.org/screenshots/index.html and PCB:
http://www.geda.seul.org/tools/pcb/index.html
see also http://www.geda.seul.org/
http://libarynth.org/cgi-bin/view/Libarynth/
see:
http://www.iro.umontreal.ca/~feeley/
and PICBIT: A Scheme System for the PIC Microcontroller
http://www.iro.umontreal.ca/~feeley/papers/sw03.pdf
also ref. Otto Roessler crash transcript at:
http://libarynth.org/cgi-bin/view/Libarynth/:2005
http://www.cs.utexas.edu/users/moore/acl2/v3-0/distrib/acl2-sources/books/workshops/1999/vhdl/
quote:
This directory contains the supporting files for Chapter 11, "Using Macros to Mimic VHDL", by Dominique Borrione, Philippe Georgelin, and Vanderlei Rodrigues, in "Computer-Aided Reasoning: ACL2 Case Studies", edited by M. Kaufmann, P. Manolios, J Moore (Kluwer, 2000, p.167-182).
and:
File fact.lisp is the example in Figure 1. It is the description of the circuit that computes the factorial function, using two concurrent processes. It uses the macros defined in the preceding file.
XSTEND and own FPGA expansion board pin details:
own interface:
8 IN 8 OUT (IN into voltage divider and both by way of 74hc245 transceiver
TOP (4 pin VGA interface)
1: GND
2: 5V
3: VSYNC
4: HSYNC
FPGA XSTEND: ref to FPGA pins (xsa-200/xsa-3s1000):
VERTICAL LINE FROM TOP:
0-7: IN
0: A5/F15
1: F14/P12
2: P9/J1
3: R9/H1
4: T9/H3
5: T7/G2
6: B9/K15
7: A9/K16
0-7: OUT
0: M7/E2
1: R6/E1
2: N7/F3
3: P7/F2
4: R7/G4
5: T14/G3
6: P8/G1
7: T8/H4
(both above as bi-directional I/O ports - extra 16 IN should be available)
0-7: MISC
1: GND
2: 5V
3: VSYNC
4: HYSNC
but all inputs must be tied down (by connection to FPGA)
http://www.stanford.edu/class/ee183/verilog/183lib.v
with 10K resistors on inputs, 5.6K 5v to collector
the NAND inputs must normally be logic 1 to avoid affecting the latching action, the inputs are considered to be inverted in this circuit.
it is forbidden to have both inputs at a logic 0 level at the same time. That state will force both outputs to a logic 1, overriding the feedback latching action. In this condition, whichever input goes to logic 1 first will lose control, while the other input (still at logic 0) controls the resulting state of the latch. If both inputs go to logic 1 simultaneously, the result is a "race" condition, and the final state of the latch cannot be determined ahead of time.
http://www.play-hookey.com/digital/rs_nand_latch.html again
Pyastra: python assembler translator (for PIC micros):
http://pyastra.sourceforge.net/
To construct components from HDL description in Xilinx WebPAck ISE:
Design utilities -> create schematic symbol
[further notes on Steele and Sussman's LispCPU]
1] Microcode:
quote [p35]:
Each of the two parts, EVAL and GC, is itself divided into two parts: registers and controller. The registers provide storage for type/pointer words, and are connected by a common bus in each part. Each controller is a finite-state machine implemented as a PLA, plus some random logic. Each PLA is organised as a micro-code ROM, addressed by a "Micro-PC" and yielding a set of control signals, including register controls and a new micro_PC indicating the next state.
signals enumerated on p36
p39. [SIMPLE Microcode] There are five kinds of operation EVAL can request from the GC (which give EVAL the step-eval signal to advance):
NOP, CAR/CDR, CONS/NCONS, RPLACD and load/store Q (one of GC's registers).
p40:
[quote]
The CONS operation accepts a car pointer from the E bus, takes the contents of Q to be the cdr pointer and then allocates a new two-word cell containing the car and cdr. A pointer to the result, with type 0 (list) is left in Q.
The Microcoded PLA is produced by software from the assembly listing (p48+) produced by the micro-assembler software from the listing (p43+)
2] The register cell
[p63]
One-bit register cell. The signal LD during O/1 loads the cell from the data bus. The signal RD during O/1 drives the bus from the cell. The cell is refreshed during O/2.
the high- low- level overlap we are interested in
in terms of a methodology of description (code, the diagram, a description of behaviour, software generation of HDL)
after: Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode
Guy Steele and Gerald Sussman
(http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT
see: 
1] Architecture reflectes language structure
2] The overlap of high level and machine language is also dictated by necessity to manipulate program as data
3] Programs are represented as nested Lisp data structures -> as a tree of linked records subject to a recursive tree walk
4] Lists are represented by records each of which contains 2 pointers to other records - car and cdr
5] The type field associated with each pointer is used to encode opcodes and return addresses
6] p17 implementation:
7] Two consecutive words of memory hold a list cell - each word can hold a type field and an address field (an address referenced within linear memory)
8] The evaluator and the storage manager as individual processors each with a state machine controller and a set of registers
contents of any register is address field and type field
9] p32 evaluation and procedure call (type 6):
We have a 3-bit type field which provides 8 opcodes (recall 7 as quotation) - address part of a word has different function depending on type (6 is procedure call).
quote:
The evaluation of type 4 (procedure) results in a pointer to the newly allocated word pair. This pointer has type 3 (closure). The car of the pair contains the cdr of the procedure: this is the code body of the procedure. The cdr of the pair contains the current environment.
and:
A procedure call (type 6) is the most complicated... It is a list of indefinite length, chained together by cdr pointers. Each cdr pointer except the last MUST have type 0 (list). The last cdr pointer should have a zero address and a non-ZERO type. This last type specifies the operation to be performed. In CDRing down the list, SIMPLE evaluates each of the expressions in the car, saving the resulting values. These values are available as arguments to the operation to be performed.
operations in tyoe here such as car, cdr, cons, atom, progn, list and funcall
10] further question of recursion in hardware by way of closures:
A closure combines the code of a function with a special lexical environment bound to that function (scope).
5v (TTL a la 74xxxx) to 3.3v (FPGA)
The second thing to do is to insert resistors between the output signals of your 5V circuitry and the gluion's 3.3V inputs. 1k Ohm will do. Furthermore you will need a clamping diode with the anode at your input pin, the cathode tied to 3.3V.
also for matrix 8x8 (chess computer interface):
Some details on the above schematic for the curious: the basic principle of a switch matrix is time-division multiplexing. This is denoted by the pulse diagrams to the left side of the SMR pins where you can see that first SMR0 is pulled low while all other SMR lines are kept high. The system then checks at which SMC pins the pulse arrives, i.e. it now knows which buttons of row 0 are held down. The process is then repeated for each row before re-starting the cycle. This is done at such a high frequency that even the shortest button closure is registered.
The resistors above the SMC pins are internal to the FPGA, i.e. you don't have to supply them yourself. They were implemented to keep the inputs from floating. As a consequence the Switch Matrix is operating in negated mode, i.e. diodes being "reversed" and pulses going down instead of up. However, this should be of no concern to the user, as long as you connect the diodes as shown above.
see: http://www.glui.de/prod/gluion/manual/gManMain.html
using FPGA for H and V sync
(for RGB from Schmitt triggers remember to link GND from board(s) to box)
~/piksel/fpga_src/tutorail2/
latest .bit as tutorial.bit
FPGA Pins:
Hsync: 85 out
Vsync: 86 out
Input: Output: all bi-directional
0: 67 12
1: 39 13
2: 44 19
3: 46 20
4: 49 21
5: 57 22
6: 60 23
7: 62 26
1] Salo (or any other film) modelled as/in Lisp process with a necessary overlap of (changed) language, structure and quotation - active language ie. that we do not simply slot the events of the film into an established framework but rather map the processes as/and characters.
2]. FPGA extension board tests (+5v) + VGA (need more headers). also test chess matrix interface. PCB photoboards. Daniel Paul Schreber. Notes...
3] Lisp cell structure to expand on. in the CPU/FPGA. a symbol
4] To collate the instruction set and the fictional data sheet with addition now of Alice instructions - Alice data bus or transmission lines ( And after that other voices went on (What a number of people there are in the carriage!' thought Alice), saying, `She must go by post, as she's got a head on her -- ' `She must be sent as a message by the telegraph -- ' )...
instructions such as "off with her head" stack head. Salo quotation cells
If brittle. Uses 74LS245 8 Bus-Transceiver for input (but 245 also can be controlled as to direction.) - potential expansion board for FPGA or schmitt triggers using these
74LS374 8 bit D-register for output
+ other logic including 74LS139 2 bit de-multiplexer
TODO: voltage dividers and possible 245s for FPGA extension board
1) J.G Ballard's Atrocity Exhibition as closest to an (expanded, to some extent architectural) instruction set for an imaginary CPU.
yet to be codified
2) circular memory (bubble is similar).
(to test IOE expansion board)
Of interest here is the ghosting of registers:
There are two sets of six general purpose registers + accumulator and flag registers (duplicate set swopped (values exchanged) by the Exchange instruction) - "The alternate set allows operation in foreground-background mode or it may be reserved for very fast interrupt response."
(From Z80 product specification).
Further 16 -bit wide registers for index, stack pointer,program counter and split (down to 8-bit) interrupt and memory reset. Also interrupt and other flip-flops.
Instruction set:
divided into categories, and described as to mnemonics and opcode
also addressing mode
LD r,r'
EX DE,HL
INC r
NEG
NOP
ADD HL, ss
RLC r
BIT b, r
JP nn
CALL nn
IN A, (n)
see also: http://www.z80.info/#BASICS_INST
also:
Binary form of opcodes
Example: LD r,r'
the 8-bit binary opcode is
01dddsss
...where "ddd" is a three-bit field specifying the destination,
and "sss" is a three-bit field specifying the source.
is shown below as
r r'
01 xxx xxx
overmapping Salo/Sadean life coding onto instruction sets
in the first instance (or with Alice/Looking Glass/Ripper whole codified mapping - to commence in process).
to start by way of circles as registers: circle of manias, circle of shit, circle of blood (with Pasolini borrowing from Dante's nine circles of hell).
As artefacts for piksel. NDR system (German) from GRAF electronics.
Working with HEXIO2 display and data entry board, SBC3 (Single board computer) main Z80 board with EPROM (for example programs and CP/M) and 8K RAM. Also IOE extension board with additional logic and prototyping area.
To program:
1] Press SPE. Type in memory address (default for code is 8100). Hit CR. Type in hexadecimal for translated opcode/addressee. + to advance in memory.
2] START followed by start address to commence execution.
We can also examine registers, ports, step through program and so on.
1] Do we use Schmitt triggers on I/O to provide logic levels (and then limit these with series resistor or voltage divider)?
2] or just use voltage divider in concert with 100 Ohm current limiter
3] or present both options on an expansion board
Test this for VGA throughput!
/usr/bin/mencoder -of mpeg -mpegopts format=dvd -srate 48000 -ofps 25 \ -ovc lavc -oac lavc -lavcopts \ vcodec=mpeg2video:vrc_buf_size=1835:keyint=15:vrc_maxrate=9800:vbitrate=4900:aspect=16/9:acodec=ac3:abitrate=192 \ test.avi -o test.mpeg2
Its expansion into an 8 bit register (8 simultaneously clocked flip-flops)
or, a 4-bit shift register (data is passed along the chain)
or, a 4 bit counter
1] Can we directly wire analogue signal across the FPGA (say from I/O pin to VGA resistors/input)?:
Using wires and assign. To test.
2] Limiting and/or isolation. All voltages < 3.3v
3] 8 bit to 8 bit - 8 cells or 8x8 matrix of cells. life, cellular automata - that matrix.
Replicated cells composed of micro-structures below:
4] Structures and/or instructions for the CPU:
a) Large Glass - Duchamp. A mechanism (in space).
b) The boudoir/bedroom. A singular eye.
c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.
d) Doubling/ghosting of gates - twinned Alice CPU
e) Further: a passage, quotation, representation. observer embedded
5] Gate diagrams (NOT, AND, NAND, OR, NOR) as artefacts:
6] Gate as switch. see diagrams for transistor multiplex switch symbol in a circle.
Switching across our non-optimal models.
Elaboration of physical circuits (for playing) alongside FPGA - headers and pin extension, break out. Coincident also with software (Lisp) simulation. Machine describing itself, its own coincident layers of active voltage. Reference SICP:
A Simulator for Digital Circuits:
http://mitpress.mit.edu/sicp/full-text/sicp/book/node64.html
and streams: http://mitpress.mit.edu/sicp/full-text/sicp/book/node72.html
7] S/R set-reset flip-flop:
for HDL see: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff
D. flip-flop:
Both based on the NAND gate - a principle of exclusion of the twin (the equivalent/identical binary pair - two ones). Thus of difference enabling a memory. Memory in an active circuit dependent always on current flow. In D flip-flop the clock line straddles the doubled NAND, with a replication of the signal enabling the difference.
Two snakes bite each others tails.
http://www.geocities.com/:/2072/cpudes.htm
and
http://www.geocities.com/:/2072/verilog.htm
see also:
http://www.mindspring.com/~tcoonan/risc8doc.html
http://www.mindspring.com/~tcoonan/pic.v
Using code from:
http://www.stanford.edu/class/ee183/handouts.shtml
we can do very simple sync and when asserted (when we can write as is visible) we can write 6 bits of piksel data (RGB 2 bits for each). next step generate video or connect prototype board pins direct to VGA (thru FPGA? as it has its own 33ohm series resistors or we just send sync out to proto pins and hardwire VGA)
ultimate black box:
dual CPUs ghosted...
as per waves and xxxxx_at_piksel:
After Artaud, the CPU (central processing unit) and its double mimes The Theatre and its Double. On the one hand, there is the System or entropic operation of a necessarily cynical machine for living, an atrocity exhibition, on the other hand the specification of an artistic CPU for life coding.
This is precisely the twinned instruction set we need to devise for multiple CPUs exposed as our 8 bits (one/zero), our pulses for an architecture which is somehow composed from diagrams.
we can just generate sync from say PIC based sync code
http://yusoft.kulichki.net/english/pic/my_proj.htm
and run straight into voltage dividers to VGA connector as below
FPGA switches itself
concurrent exposed communicative (promiscuous) (instruction?) modules
exposed by way of PWM or rather single bits which can then be output as audio or as video / composite (with sync generation in software - we have an NTSC example but colour PAL is more complex - also using small resistor ladder to output) or VGA (we have vgahdl example code which looks quite simple)
and also using voltage dividers provided by resistors:
quote
Pins 13 and 14 of the VGA connector (HS and VS) are digital signals, so can be driven directly from two FPGA pins.
Pins 1, 2 and 3 (R, G and B) are 75 ohm analog signals. With 3.3V IOs, use three 270 ohm series resistors. The resistors form voltage dividers with the 75 ohm resistors in the monitor inputs so that 3.3V become 3.3*75/(270+75)=0.72V, pretty close to 0.7V. Driving these 3 pins with different combinations of 0's and 1's gives us up to 8 colors.
Ground pins are pins 5, 6, 7, 8 and 10
multiplexed internals, and only internals data access. shared or no registers - how to specify such a design...
Visually:
1] That we can draw components and connect them within a schematic entry which ranges across low and high level (black-boxed) components both from a common library and generated from our own code (using the Create Schematic Symbol entry under Design Utilities in Process).
We can access such created components under the filepath in Categories in the schematic editor when we create say a new overarching design which specifies the connection of large-scale modules/components.
2] That we can (when we select new source) choose further modules from the IP (Coregen & Architecture Wizard) option - this are classified as to various categories, including DSP, math functions, memories, and basic elements such as counters and multiplexors.
3] At the same time using the View/Edit Placed Design (Floorplanner) (under Processes: Implement, Place and Route) we can see how the logic circuitry and I/O are assigned to the CLBs (configurable logic blocks).
From the Floorplanner toolbar we can toggle ratsnest (connection) display and zoom in and out.
Macro and micro views:
http://www.frank-buss.de/lispcpu/index.html
which defines in Verilog output (pins) RAM (on the FPGA), program counter, registers and very basic evaluator (which evaluates hard-coded instructions) - the output in this instance is to slowly flash one LED! This example demonstrates I/O pin assignment
further SDRAM:
http://www.xess.com/appnotes/an-071205-xsasdramcntl.html
Describes/implements/wraps up an SDRAM controller core.
audio:
In the instance of audio perhaps rather than dealing with the on-board audio codec of the XSTend borad, perhaps we should make use of raw 8 bit I/O from prototype area (to primitive soundcard or schmitt trigger box) - prototype area can be connected to adjacent J4 which accesses all the prototype pins from the XSA-50 header (we can look this up in the manual for assignment).
and video:
We can use VGA (some cores/sample projects - note that a useful experiment would be to send voltages (0->0.7v) for RGB signals raw to monitor... or we can use video out on XSTend board, or just resistor ladder from XSA-50 data pins as suggested in ntsc example on:
http://www.xess.com/ho03000.html
where we find all project examples.
Boards used:
XSA-50 development board (Xilinx XC2S50 FPGA (Spartan II/2), 128K Flash memory for FPGA bitstream, 8 Megabyte DRAM).
and XSTend board V3.0 (XST-3.0) from XESS
(stereo codec, dual channel analogue I/O, video decoder, ethernet, usb, rs-232, ide)
see:
http://stewks.ece.stevens-tech.edu/CpE487-S05/HomeworkF04/:/hlisiteB/NotesForXessBoard.html
... example code is in VHDL.
see also free_fpga_guide for some background and install of Xstools from XESS:
link: Xstools RPM: http://www1.cs.columbia.edu/~sedwards/software/xstools-4.0.3-1.i386.rpm
x____
stages:
0] Re-install WebPack (this version 8.2.02i) from Xilinx:
http://www.xilinx.com/webpack/
1) using web-based installer which is a very lengthy process.
2) then we use the opening lines from the shell script at:
http://panteltje.com/panteltje/fpga/index.html
(which outlines solely commandline use of Xilinx toolset.)
mkdir /usr/local/lib/xilinx/ cp ~/Xilinx/bin/lin/*.so /usr/local/lib/xilinx/ echo /usr/local/lib/xilinx >> /etc/ld.so.conf ldconfig and: export XILINX=/root/Xilinx
then we can run bin/lin/xst commandline program
for full GUI:
bin/lin/ise
1] connect parallel port. start laptop. power up XSA-50 board. launch xstest from commandline to test:
xstest -b xsa-50
launch WebPack (command: Xilinx/bin/lin/ise)
2] create new project (here we define the device and the design flow)
Over the above tutorial and past work there is now a new project wizard - we skip over behaviourals and ports:
we create leddec (LED decoder as per tutorial)
3] insert VHDL module (describe/enter (in) VHDL code)
Double click on leddec in sources and edit templated source code.
4] synthesize - highlight module filename .vhd
Click on Synthesize-XST in Processes. Successful
5] implement design process eg. place and route
Highlight and then select Implement Design in Processes
6] new source - implementation constraints (I/O pins assigned as below). then Create Timing Constraints, then port tag:
Select leddec in Sources, right click and select New source following the example names as leddec_ucf, associate this with leddec and then expand User Constraints item in processes to access Create Timing Constraints - once there (new window opened for constraints editor) we can select the Ports tab to access port name attributed in our VHDL and hopefully assign pins (location) as gathered from XESS manual.
In this instance unable to enter text into Location field...
Rather we must choose Assign Package Pins from User Constraints in Process and enter pins here - then these can be double-checked in the above editor.
7] rerun implement design
Successful!
8] generate bitstream - Generate Programming File
Successful!
9] use xsload to download over parallel port - .bit file (in our project file as defined:
xsload -b xsa-50 -fpga ~/piksel/fpgatests/leddec/leddec.bit Configure FPGA: Downloading leddec.bit:fst field: ignoring 9 bytes 100%
(strangely enough produces an error when run from eshell)
in the first example LED decoder from the above URL the xsport utility is used to send bit patterns to the parallel port:
eg:
xsport 101
b) understanding of RAM and I/O pin access with XTEND board - again using example code. also perhaps audio and simple video
I/O pin access (which is used within Implementation Constraints (ucf file)) is simply a matter of looking up pin assignments in the manual. The example above also gives some advice.
Design of LISP-Based processors ... or, LAMBDA The Ultimate Opcode
Guy Steele and Gerald Sussman (http://repository.readscheme.org/ftp/papers/ai-lab-pubs/AIM-514.pdf ) 1979, MIT
To quote from the opening abstract:
We present a design for a class of computers whose 'instruction sets' are based on LISP. LISP, like traditional stored-program machine languages and unlike most high-level languages, conceptually stores programs and data in the same way and explicitly allows programs to be manipulated as data. LISP is therefore a suitable language around which to design a stored-program computer architecture. LISP differs from traditional machine languages in that the program/data storage is conceptually an unordered set of linked record structures of various sizes, rather than an ordered, indexable vector of integers or bit fields of fixed size. The record structures can be organised into trees or graphs. An instruction set can be designed for programs expressed as such trees. A processor can interpret these trees in a recursive fashion, and provide automatic storage management for the record structures.
further - an architecture and an instruction set are specified, fabrication of a VLSI prototype microprocessor is described.
1) LISP as a high-level machine language. Given that "LISP reflects the structure of program expressions in the structure of the data which represents the program." and also given that data and programs are equivalent and can equally be manipulated (within the "incestuous" realm of compilers and interpreters).
2) Tree structure rather than linear vector of instructions which can be indexed using counters and the like. Evaluation by recursive tree-walk.
3) Lisp atoms and lists are described in fine detail with examples prior to the exposition of a meta-circular LISP interpreter (ie. it is written in LISP and can interpret itself).
4) APPLY within this simple interpreter... in the case of primitive procedures:
"... primitive symbols are not to be confused with the atomic symbols used as their names. The actual procedure involved in the combination (car x) is not the atomic symbol CAR, but rather some bizarre object (the value of the atomic symbol CAR) which is meaningful only to PRIMOP-APPLY."
(thus further into the appendix the magic of execution is microcoded)
5) State machine implementation:
An interpreter in the form of a state machine controller. (rendering explicit as a control mechanism that which the recursive LISP interpreter hides - state information that must be saved on each recursive invocation).
Registers and a list memory system.
The evaluator in Lisp has five global registers which simulate the registers of a machine
EXP - hold expression or parts of under evaluation ENV - holds pointer to environment structure (context) VAL - value developed in evaluation of expressions ARGS - list of evaluated arguments CLINK - pointer to top of the list structure which is the control stack
Further LISP code such as EVAL-DISPATCH implements the simulation
6) Representing LISP data.
"Lists are normally represented by records each of which contains two pointers to other records. One pointer is the car and the other is the cdr."
(A (B C) D) becomes
_ _ _ _ _ _
|.|.+ -> |.|.+ -> |.|.+--> NIL
- - - - - -
| | |
v | v
A v D
_ _ _ _
|.|.+ -> |.|.+--> NIL
- - - -
| |
v v
B C
Pointer representation is unimportant. We give pointer to memory system and it returns the context of the record pointed to. A type field is associated with each pointer.
7) The state machine implementation is combined with typed pointer dispatch to form an interpreter which can be implemented in hardware (p. 15)
8) Storage management:
The system is divided into:
a) a storage system which "provides an operator for he creation of new data objects and also other operators (such as pointer traversal) on those objects."
b) EVAL (program interpreter) which "executes programs expressed as data structures within the storage system"
in classic Von Neumann style.
The storage manager here makes a "finite vector memory appear to the evaluation mechanism to be an infinite linked-record memory". Thus a garbage collector is implemented.
9) Physical layout of the prototype processor
"The evaluator and the storage manager are each implemented in the same way as an individual processor. Each processor has a state-machine controller and a set of registers. On each clock cycle the state-machine outputs control signals for the registers and also makes transitions to a new state."
...
"The contents any register is a pointer (8 bits in the prototype) and a type field (3 bits in the prototype). The registers of a processor are connected by a common bus (E bus in the evaluator, G bus in the storage manager)
....
"Each state-machine controller consists of a read-only memory (implemented as a PLA), two half registers (?) (clocked inverters, one at each input and one at each output), and some random logic (eg. for computing the next state)... two phase non-overlapping clock signals..."
1- registers are clocked. next state is computed
2- next-state signals appear and are latched
all signals from the controllers can be multiplexed onto twelve probe lines
10) Discussion
There is no ALU.
Possible addition of complex processors/devices on the external memory bus with LISP processor serving as controller.
At the same time talks of a layered approach wherein a line can be drawn at arbitrary points within a tower of abstraction = a boundary between evaluator and storage manager
"... a hierarchy of interpreters running in [a] virtual machine. Each layer implements a virtual machine within which the next processor up operates."
such a boundary also exhibits an arbitrary distinction between hardware and software. also the overlap:
"Each of the layers in this architecture has much the same organisation: it is divided into a controller ("state machine") and a data base ("registers"). There is a reason for this. Each layer implements a memory system and so has state; this state is contained in the data base (which may be simply a small set of references into the next memory system down (own note: no operation but only a mapping)). Each layer also accepts commands from the layer above it, and transforms them into commands for the layer below it; this is the task of the controller."
also in talking of analogies between common CPU and CPU here:
"We may loosely say that there are two addressing modes in this architecture, one being immediate data (as in a variable reference), and the other being a recursive evaluation. In the latter case, merely referring to an operands automatically calls for the execution of an entire routine to compute it!"
11) History of VLSI implementation
Typed pointers treated as instructions, with the types as "opcodes" to be dispatched on by a state machine...
Rough sketch of building blocks:
PLA library array cells, simple replicated register cells assembled using (LISP-based) software
12) Conclusion
A CPU "... organised purely around linked records, especially in that the instruction set is embedded in the organisation."
Finally concludes that just as the LISP tree data representation informs this particular instruction set and thus the CPU architecture (for it is not just a question of representation but also changing the means of manipulation), so other representations (for example graphs) or storage organisations could be examined.
13) Appendix - Prototype Lisp Processor Technical Specifications
For later examination.
so far... The Instruction Set:
The 3 byte type field supplies 8 "opcodes":
from 0=constant list to 7=quoted constant
Address part of the word has different purposes dependent on type.
Procedure call (type 6) is the most complicated of all:
"It is a list of indefinite length, chained together by CDR pointers
xx_____
Also of note here is the use of transistors and resistors (in this case depletion-mode transistors) which can be used to construct logic gates.
see also GC probe mux and multiplexor p61,62 - a grid of wires with transistor across for probes
register cell p 63
flip-flop:
flip-flop as (bistable, in the case of counters, registers and memory) multivibrator
http://www.eelab.usyd.edu.au/digital_tutorial/part2/flip-flop01.html
inductor:
changing current in an inductor produces an EMF in the inductor which opposes the current change...
-> reactance (ohms) whuch is the ac equivalent of resistance and in case of inductor is effected by frequency (high frequency high reactance)
The Design of an M6800 LISP Interpreter, S Tucker Taft, BYTE August 1979
(notes for piksel, instruction sets as steps towards Lisp CPU or any kind of artistic CPU - an examination of hardware-based means of representation. At what point the necessary reduction (or why it is considered as such) into hardware makes sense. Or to keep all levels as a simultaneity. Comparison of high-level with instruction sets. At the same time some way - borrowing from the Lisp CPU - that we can eavesdrop in audio fashion on all internals of the CPU, not just registers a la self.c (own code see software) but also data paths. Indeed if such paths ans such an exposure are implied through a parallel switching architecture. The FPGA is attractive precisely as RECONFIGURABLE architecture or matrix rather than as RECONFIGURED.)
1) Underlying representation of lists using dotted pairs (two address cells). The left cell points to the first element of a list, and the right cell to the rest of the list. NIL is used to signify end of the chain. CONSing two atoms gives a dotted pair with CDR of final dotted pair as non-NIL atom.
(see also diagrams on:
http://www.gigamonkeys.com/book/they-called-it-lisp-for-a-reason-list-processing.html
)
2) READ, EVAL and PRINT loop
Internal representation of the list (the program) is called a form here - the form is evaluated according to the convention that the first element of such a list specifies a function, with the rest of the list as arguments.
3) Into implementation:
BIGLUP LDX PRMPAT get prompt atom
JSR PATOM print the atom
JSR READ read the form - result is in x reg
JSR EVAL eval the form - result is in x reg
JSR PRINT
BRA BIGLUP
PATOM is a subroutine, also used by PRINT when a form is tested as an atom.
M6800 index (X) register - 16 bits long use for all object representations/forms
Dotted pairs must hold two forms - thus 32 bits (4 consecutive memory bytes)
Internal representation for atoms:
For symbolic atoms two items of information are needed:
thus 4 bytes chosen with first 2 as memory address of print name and third of fourth holding value (form) of the atom
A way to distinguish dotted pairs from atoms is needed:
In this instance all dotted pairs and atoms are aligned on 4 byte boundaries which means that we can use the lowest two bits 00 01 to encode type and garbage collection (GC) information.
With numeric atoms name determines value and hence only name (or value) needs to be specified. Representation was chosen with high order bit set, 14 bits numeric value and 1 for GC (seeing as only 0000 through 7FFF is used for atoms and dotted pairs storage bit so when forms specify this high order bit is free.
Special representation for the NIL atom High order byte is zero (which rules out 256 byte page starting at zero).
x_______
A linked list (called OBLIST) of all defined symbolic atoms is used for example by READ and also the EQ function. READ checks prior to allocating 4 byte cell for atome of given print name. If found, returns form specifying the pre-existing atom. Otherwise, copies name into name storage area, allocates 4 byte cell, inits left cell to point to name and right to NIL and returns form.
x_____
READ function
Builds up internal representation - allocating dotted pairs and atoms. If expression is a list READ returns the first dotted pair.
RATOM does the work of allocating new cells as above. Deals with parentheses with recursive calls to READ.
(code p143)
PRINT function
Takes a single form as argument, and types the value as fully parenthesised LISP expression.
EVAL function
The heart of the matter.
EVAL accepts one form as argument and evaluates it according to the convention:
"the value of NIL is NIL, the value of a numeric atom is itself, the value of a symbolic atom is the form associated with the atom, and the value of a list is determined by applying the function specified by the CAR of the list to the list of arguments which make up the CDR of the list."
SUBRs and LAMBDAs: SUBRs as built in functions written in machine code (eg. CAR< CDR< PATOM). LAMBDAs are user defined.
The system here treats the bytes which make up the machine code of the SUBR as the print name of the atom. SUBR specified with dotted pair and car as atom SUBR. Machine code is also prefixed with a special string.
(p147 code listing)
in a GNU E