ap/xxxxx

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for xxxxx_publication working on some spatialisation of Zuse's 20:33 (research#40)

day four electronics: 20:29 (2006.08.03:8 research#39 tech_notes#181)

1) tie fence (if it is conductor) to one arm of potentiometer on 40106

circuit constructed

2) chain of floating 74x240s (using all 8). 2 buffer/invretors feed via 0.22 uF (marked 224) into each other and with an LED across the 2nd buffer/invertor and a 1M variable resistor connecting 2 inputs (or only across 2nd as with LED). interesting oscillations... also

pins 1 and 19 tied to gnd to enable the invertors.

range of possible connections.

3) Schmitt trigger from Beam article: positive/negative feedback

negative feedback - 74x240 invertor with resistor across input to output - towards balance point is half Vcc - 240 transmits high frequency waves (see CMOS radio transmitter)

positive - adds to input and steers away from 1/2 Vcc balance zone

240 has single threshold - 14 has two (positive and negative going as per hysteresis)

using negative feedback (resistor from output to input and say 1M input resistor) we can alter hysteresis thresholds

(if it was non-inverting like a 245 we could create + feedback or with 2x 240 in series and with resistor across both)

opcode is selection of a circuit with ref to the ALU 16:19 (2006.08.03:7 research#38 xxxxx_at_piksel_notes#9 tech_notes#180)

for example:

http://www.cellmatrix.com/entryway/products/applications/8bitALU.html

and:

http://www.cs.trinity.edu/About/The_Courses/cs301/04.computer.circuits/04.comp.cir.html

is interesting as it uses Scheme to model the ALU/logic

Konrad Zuse 16:04 (2006.08.03:6 research#37 xxxxx_at_piksel_notes#8 tech_notes#179)

http://tams-www.informatik.uni-hamburg.de/applets/hades/webdemos/05-switched/20-relays/zuseadd.html

(but need to find more schematics)

http://web.cecs.pdx.edu/~harry/Relay/Overview.txt

http://hjs.geol.uib.no/zuse/zusez1z3.htm

Calculating Space. Rechnender Raum. Zuse - cellular automata

cellular automata and fpga as possibility. language.

FPGA, schematics, 8 bit, CPU for general research and cover image 13:07 (tech_notes#178)

http://germanium.cs.wustl.edu/ToyCPU/toy_cpu.html

http://www.holmea.demon.co.uk/Mk2/Schematics.htm

http://www.zetetics.com/bj/papers/piscedu2.htm

http://cis.k.hosei.ac.jp/~yamin/lectures/organization/single-cycle.html

http://www.iit.edu/~kottven/project2.htm

http://www.pjrc.com/tech/osu8/sch/osu8.html

http://www.physics.mcmaster.ca/phy4d6/Lab/chapter6.htm

http://en.wikipedia.org/wiki/User:B_rip

http://www.vttoth.com/vicproc_block.htm

and an old reminder:

http://aggregate.org/:/TARIQ_SLIDES/paper.html

http://www.cs.umbc.edu/~squire/cs313_lect.html

http://zxgate.sourceforge.net/ 11:58 (tech_notes#177)

http://www.torlus.com/index.php?Fpga/2005/12 11:47 (tech_notes#176)

http://www.z80.info/z80test0.htm 11:46 (tech_notes#175)

VLSI: 11:32 (2006.08.03:1 research#36 xxxxx_at_piksel_notes#7)

very large-scale integration

http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/toc.html

particularly:

http://lsiwww.epfl.ch/LSI2001/teaching/webcourse/ch06/ch06.html