--> ap/xxxxx


Dissect the Z80 instruction set and re-map 20:36 (2006.09.19:3 research#1 xxxxx_at_piksel#2)


Z80 development board(s) 20:34 (2006.09.19:2 tech_notes#276 xxxxx_at_piksel#1)

As artefacts for piksel. NDR system (German) from GRAF electronics.

Working with HEXIO2 display and data entry board, SBC3 (Single board computer) main Z80 board with EPROM (for example programs and CP/M) and 8K RAM. Also IOE extension board with additional logic and prototyping area.

To program:

1] Press SPE. Type in memory address (default for code is 8100). Hit CR. Type in hexadecimal for translated opcode/addressee. + to advance in memory.

2] START followed by start address to commence execution.

We can also examine registers, ports, step through program and so on.

Questions regarding 8 I/O to FPGA: 18:55 (2006.09.19:1 tech_notes#275 fpga#10 xxxxx_at_piksel_notes#35)

1] Do we use Schmitt triggers on I/O to provide logic levels (and then limit these with series resistor or voltage divider)?

2] or just use voltage divider in concert with 100 Ohm current limiter

3] or present both options on an expansion board

Test this for VGA throughput!