latest mencoder DIVX to DVD: 20:58 (tech_notes#274)

/usr/bin/mencoder -of mpeg -mpegopts format=dvd -srate 48000 -ofps 25 \
-ovc lavc -oac lavc -lavcopts \
vcodec=mpeg2video:vrc_buf_size=1835:keyint=15:vrc_maxrate=9800:vbitrate=4900:aspect=16/9:acodec=ac3:abitrate=192 \
test.avi -o test.mpeg2

The CPU and its double: 14:24 (2006.09.16:4 xxxxx_at_piksel_notes#34 research#80)

after Artaud - the CPU of cruelty:

Of relevance:


It is a question then of making the theater, in the proper sense of the word, a function; something as localized and as precise as the circulation of the blood in the arteries...


Meanwhile new means of recording this language must be found, whether these means belong to musical transcription or to some kind of code...

As for ordinary objects, or even the human body, raised to the dignity of signs, it is evident that one can draw one's inspiration from hieroglyphic characters, not only in order to record these signs in a readable fashion which permits them to be reproduced at will, but in order to compose on the stage precise and immediately readable symbols.

On the other hand, this code language and musical trans-cription will be valuable as a means of transcribing voices.


We abolish the stage and the auditorium and replace them by a single site, without partition or barrier of any kind, which will become the theater of the action.

4] THE INTERPRETATION: The spectacle will be calculated from one end to the other, like a code (un langage). Thus there will be no lost movements, all movements will obey a rhythm; and each character being merely a type, his gesticulation, physiognomy, and costume will appear like so many rays of light.

and within THE PROGRAM:

  1. A Tale by the Marquis de Sade, in which the eroticism will be transposed, allegorically mounted and figured, to create a violent exteriorization of cruelty, and a dissimulation of the remainder.

allegorically mounted within gthe CPU

Also with regard to the D flip-flop: 13:10 (2006.09.16:3 tech_notes#273 fpga#9 research#79 xxxxx_at_piksel_notes#33)

Its expansion into an 8 bit register (8 simultaneously clocked flip-flops)

or, a 4-bit shift register (data is passed along the chain)

or, a 4 bit counter

Ideas/questions: 13:00 (2006.09.16:2 tech_notes#272 fpga#8 research#78 xxxxx_at_piksel_notes#32)

1] Can we directly wire analogue signal across the FPGA (say from I/O pin to VGA resistors/input)?:

Using wires and assign. To test.

2] Limiting and/or isolation. All voltages < 3.3v

3] 8 bit to 8 bit - 8 cells or 8x8 matrix of cells. life, cellular automata - that matrix.

Replicated cells composed of micro-structures below:

4] Structures and/or instructions for the CPU:

a) Large Glass - Duchamp. A mechanism (in space).

b) The boudoir/bedroom. A singular eye.

c) Simulated world (billiard ball universe). Kopf. Mushroom cloud neurons.

d) Doubling/ghosting of gates - twinned Alice CPU

e) Further: a passage, quotation, representation. observer embedded

5] Gate diagrams (NOT, AND, NAND, OR, NOR) as artefacts:

6] Gate as switch. see diagrams for transistor multiplex switch symbol in a circle.

Switching across our non-optimal models.

Elaboration of physical circuits (for playing) alongside FPGA - headers and pin extension, break out. Coincident also with software (Lisp) simulation. Machine describing itself, its own coincident layers of active voltage. Reference SICP:

A Simulator for Digital Circuits:


and streams: http://mitpress.mit.edu/sicp/full-text/sicp/book/node72.html

7] S/R set-reset flip-flop:

for HDL see: http://myhdl.jandecaluwe.com/doku.php/cookbook:ff

D. flip-flop:

Both based on the NAND gate - a principle of exclusion of the twin (the equivalent/identical binary pair - two ones). Thus of difference enabling a memory. Memory in an active circuit dependent always on current flow. In D flip-flop the clock line straddles the doubled NAND, with a replication of the signal enabling the difference.

Two snakes bite each others tails.

Verilog CPU - follows use of 'case' for opcodes from lisp cpu example: 12:31 (2006.09.16:1 tech_notes#271 fpga#7)




see also: