--> ap/xxxxx


using the code here we could generate VGA sync signals 20:40 (tech_notes#266)

and also using voltage dividers provided by resistors:


Pins 13 and 14 of the VGA connector (HS and VS) are digital signals, so can be driven directly from two FPGA pins.

Pins 1, 2 and 3 (R, G and B) are 75Ω analog signals. With 3.3V IOs, use three 270Ω series resistors. The resistors form voltage dividers with the 75Ω resistors in the monitor inputs so that 3.3V become 3.3*75/(270+75)=0.72V, pretty close to 0.7V. Driving these 3 pins with different combinations of 0's and 1's gives us up to 8 colors.

Ground pins are pins 5, 6, 7, 8 and 10

FPGA as parallel CPUs 19:23 (2006.09.13:2 xxxxx_at_piksel_notes#27 research#72 tech_notes#265 fpga#4)

multiplexed internals, and only internals data access. shared or no registers - how to specify such a design...


1] That we can draw components and connect them within a schematic entry which ranges across low and high level (black-boxed) components both from a common library and generated from our own code (using the Create Schematic Symbol entry under Design Utilities in Process).

We can access such created components under the filepath in Categories in the schematic editor when we create say a new overarching design which specifies the connection of large-scale modules/components.

2] That we can (when we select new source) choose further modules from the IP (Coregen & Architecture Wizard) option - this are classified as to various categories, including DSP, math functions, memories, and basic elements such as counters and multiplexors.

3] At the same time using the View/Edit Placed Design (Floorplanner) (under Processes: Implement, Place and Route) we can see how the logic circuitry and I/O are assigned to the CLBs (configurable logic blocks).

From the Floorplanner toolbar we can toggle ratsnest (connection) display and zoom in and out.

Macro and micro views:

Successfully modified basic CPU code from: 17:29 (2006.09.13:1 research#71 tech_notes#264 xxxxx_at_piksel_notes#26 fpga#3)


which defines in Verilog output (pins) RAM (on the FPGA), program counter, registers and very basic evaluator (which evaluates hard-coded instructions) - the output in this instance is to slowly flash one LED! This example demonstrates I/O pin assignment

further SDRAM:


Describes/implements/wraps up an SDRAM controller core.


In the instance of audio perhaps rather than dealing with the on-board audio codec of the XSTend borad, perhaps we should make use of raw 8 bit I/O from prototype area (to primitive soundcard or schmitt trigger box) - prototype area can be connected to adjacent J4 which accesses all the prototype pins from the XSA-50 header (we can look this up in the manual for assignment).

and video:

We can use VGA (some cores/sample projects - note that a useful experiment would be to send voltages (0->0.7v) for RGB signals raw to monitor... or we can use video out on XSTend board, or just resistor ladder from XSA-50 data pins as suggested in ntsc example on:


where we find all project examples.